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US 6,788,573 B2Granted
Non-volatile semiconductor memory and method of operating the same
OwnerWoong Lim Choiinventor
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Abstract
The present invention discloses a non-volatile semiconductor memory device and a method of operating the same. More specifically, the present invention includes a semiconductor substrate having active and field regions, at least two non-volatile storage transistors each of which having a storage on the active region and a control gate at the storage, wherein at least two control gates are incorporated into a single control plate, and at least two selection transistors each of which corresponds to the non-volatile storage transistor, wherein each of the selection transistors connected to the corresponding non-volatile storage transistors for selecting the corresponding non-volatile storage transistors.
Claims74
A non-volatile semiconductor memory comprising:
- a semiconductor substrate having active and field regions;
- at least two non-volatile storage transistors each having a storage at the active region and a control gate at the storage, wherein each control gate is incorporated into a single control plate;
- and
- at least two selection transistors, each of which is connected to a corresponding one of the non-volatile storage transistors for selecting the corresponding non-volatile storage transistor, and wherein each selection transistor is connected in series to the corresponding non-volatile storage transistor through a PN-junction shared by the selection transistor and the corresponding non-volatile storage transistor.
1 more element
A non-volatile semiconductor memory comprising:
- a semiconductor substrate having active and field regions;
- a dielectric layer on the substrate;
- at least two non-volatile storage transistors on the substrate, each non-volatile storage transistor including a source and a drain in the substrate, a storage over the active region, and a control gate at the storage, wherein each control gate is incorporated into a single control plate and the source is shared by adjacent non-volatile storage transistors as a common source;
- and
- at least two selection transistors on the substrate, each selection transistor including a source and a drain in the substrate, a selection gate on the dielectric layer between the source and the drain, wherein the source of each of the selection transistors acts as the drain of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor.
2 more elements
A non-volatile semiconductor memory array, comprising:
- a plurality of bit lines arranged in a column direction;
- a plurality of word lines arranged in a row direction;
- a plurality of source lines arranged in the row direction;
- a plurality of control plate lines arranged in the row direction;
- and
- a plurality of non-volatile memory cells between the lines, each of the non-volatile memory cells includes,
- at least two non-volatile storage transistors each of which includes a source and a drain in a substrate, a drain formed in the substrate, a storage over the active region, and a control gate at the storage, wherein each control gate is incorporated into a control plate built in a single body and the source is shared by adjacent non-volatile storage transistors as a common source, and
- at least two selection transistors each of which includes a source and a drain in the substrate, a selection gate on the dielectric layer between the source and drain so as to be isolated from the storage, wherein the source of each of the selection transistors is the drain of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor, and selection gates of the respective cells are connected to the corresponding word lines in the row direction, the common source of a unit cell is connected to the corresponding source line extending in the row direction, the control plate is connected to the corresponding control plate line in the row direction, and the drain of the selection transistor in the cell is connected to the corresponding bit line.
5 more elements
In a non-volatile semiconductor memory including at least two non-volatile storage transistors each of which including a source in the substrate, a drain in the substrate, a storage on the dielectric layer over the active region, and a control gate at the storage, at least two control gates incorporating into a control plate built in a single body, and at least two selection transistors each of which including a source in the substrate, a drain in the substrate, a selection gate on the dielectric layer between the source and the drain to be isolated from the storage, wherein the source of each of the selection transistors is the drain of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor, a method of operating the non-volatile semiconductor memory, comprising:
- selecting one of the non-volatile storage transistors by turning on or off the respective selection transistors;
- and
- programming the selected non-volatile storage transistor using a hot carrier injection method generating hot electrons from a channel of the selected non-volatile storage transistor.
A non-volatile semiconductor memory array including a plurality of bit lines arranged in a row direction, a plurality of word lines arranged in a column direction, a plurality of source lines arranged in the row direction, a plurality of control plate lines arranged in the row direction, and a plurality of non-volatile memory cells between the lines, each of the non-volatile memory cells, comprising:
- at least two non-volatile storage transistors each of which including a source, a drain, a storage, and a control gate at the storage, wherein at least two control gates are incorporated into one control plate built in a single body and the source of adjacent non-volatile storage transistors is a common source;
- and
- at least two selection transistors each of which including a source, a drain, a selection gate between the source and the drain to be isolated from the storage, wherein the source of each of the selection transistors is the drain of a corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor, wherein the selection gates of the respective cells are connected to corresponding word lines in the column direction, the common source is connected to a corresponding source line extending in the row direction, the control plate is connected to a corresponding control place line in the row direction, and the drain of the selection transistor is connected to the corresponding bit line.
A non-volatile semiconductor memory comprising:
- a semiconductor substrate having active and field regions;
- a dielectric layer on the semiconductor substrate;
- at least two non-volatile storage transistors on the substrate each of which including a source in the substrate, a drain in the substrate, a storage on the dielectric layer over the active region, and a control gate at the storage, wherein at least two control gates are incorporated into a single control plate and the drain is shared by the adjacent non-volatile storage transistors as a common drain;
- and
- at least two selection transistors on the substrate each of which including a source in the substrate, a drain in the substrate, a selection gate on the dielectric layer between the source and the drain to be isolated from the storage, wherein the drain of each of the selection transistors is the source of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor.
2 more elements
A non-volatile semiconductor memory array, comprising:
- a plurality of bit lines arranged in a column direction;
- a plurality of word lines arranged in a row direction;
- a plurality of source lines arranged in the row direction;
- a plurality of control plate lines arranged in the row direction;
- and
- a plurality of non-volatile memory cells between the lines, each of the non-volatile memory cells including,
- at least two non-volatile storage transistors each of which having a source formed in a substrate, a drain in the substrate, a storage on the dielectric layer over the active region, and a control gate at the storage, wherein at least two control gates are incorporated into a single control plate and the drain is shared by adjacent non-volatile storage transistors as a common drain, and
- at least two selection transistors each of which having a source in the substrate, a drain in the substrate, a selection gate on the dielectric layer between the source and the drain to be isolated from the storage, wherein the drain of each of the selection transistors is the source of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor, wherein the selection gates of the respective cells are connected to the corresponding word lines in the row direction, the common drain of a unit cell is connected to the corresponding bit line extending in the row direction, the control plate is connected to the corresponding control plate line in the row direction, and the source of the selection transistor in the cell is connected to the corresponding source line.
5 more elements
A non-volatile semiconductor memory, comprising:
- a semiconductor substrate having active and field regions;
- a dielectric layer on the semiconductor substrate;
- at least two non-volatile storage transistors each of which including a source in the substrate, a drain in the substrate, a storage on the dielectric layer over the active region, and a control gate at the storage, wherein at least two control gates are incorporated into a single control plate;
- and
- at least two selection transistors each of which including a source in the substrate, a drain in the substrate, a selection gate on the dielectric layer between the source and the drain to be isolated from the storage, wherein the drain of each of the selection transistors acts as the source of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistors.
2 more elements
A non-volatile semiconductor memory array, comprising:
- a plurality of bit lines arranged in a row direction;
- a plurality of word lines arranged in a column direction;
- a plurality of source lines arranged in the row direction;
- a plurality of control plate lines arranged in the row direction;
- and
- a plurality of non-volatile memory cells between the lines, each of the non-volatile memory cells including,
- at least two non-volatile storage transistors each of which having a source in a substrate, a drain formed in the substrate, a storage on the dielectric layer over the active region, and a control gate at the storage, wherein at least two control gates are incorporated into a single control plate;
- and
- at least two selection transistors each of which having a source in the substrate, a drain in the substrate, a selection gate on the dielectric layer between the source and the drain to be isolated from the storage, wherein the drain of each of the selection transistors is the source of the corresponding non-volatile storage transistor, and each of the two selection transistors is connected to the corresponding non-volatile storage transistor for selecting the corresponding non-volatile storage transistor, wherein the selection gates of the respective cells are connected together to the corresponding word lines in the column direction, the drains of the cells are connected to the different bit lines, the control plate is connected to the corresponding control plate line in the row direction, and the source of the selection transistor is connected to the corresponding source line.
6 more elements
A non-volatile memory comprising:
- a semiconductor substrate having active and field regions;
- a dielectric layer on the semiconductor substrate;
- a first source in the active region;
- a common drain in the active region to have a first channel between the common drain and the first source;
- a second source in the active region to have a second channel between the common drain and the second source;
- a first gate and a first storage on the dielectric layer in parallel with each other over the first channel;
- a second gate and a second storage on the dielectric layer in parallel with each other over the second channel;
- and
- a control plate built in a single body over the first and second storage.
6 more elements
A non-volatile semiconductor memory array comprising:
- a plurality of bit lines arranged in a column direction;
- a plurality of word lines arranged in a row direction;
- a plurality of source lines arranged in the row direction;
- a plurality of control plate lines arranged in the row direction;
- and
- a plurality of non-volatile memory cells between the lines, each of the non-volatile memory cells including,
- a semiconductor substrate having active and field regions;
- a dielectric layer on the semiconductor substrate;
- a first source in the active region;
- a common drain in the active region to have a first channel between the common drain and the first source;
- a second source in the active region to have a second channel between the common drain and the second source;
- a first gate and a first storage on the dielectric layer in parallel with each other over the first channel;
- a second gate and a second storage on the dielectric layer in parallel with each other over the second channel;
- and
- a control plate built in a single body over the first and second storage,
- wherein the first storage, the common drain, and the control plate form a first non-volatile storage transistor, the first source and the selection gate form a first selection transistor for the first non-volatile storage transistor, the second storage, the common drain, and the control plate form a second non-volatile storage transistor, and the second source and the selection gate form a second selection transistor for the second non-volatile storage transistor, and
- wherein the selection gates of the cell are connected to the different corresponding word lines, the common drain is connected to the corresponding bit lines, the control plate is connected to the corresponding control plate lines, and the sources of the selection transistors of the cell are connected to the different source lines.
14 more elements
A non-volatile memory comprising:
- a first conductive type semiconductor substrate having active and field regions;
- a first region in the active region, the first region having a second conductive type;
- a second region having the second conductive type to have a first channel between the first and second regions;
- a third region having the second conductive type to have a second channel between the second and third regions;
- a first non-volatile storage on the first channel to be overlapped at least a portion of the second region;
- a first dielectric between the substrate and the first non-volatile storage;
- a second non-volatile storage on the second channel to be overlapped at least a portion of the second region;
- a second dielectric between the substrate and second non-volatile storage;
- a first selection gate over the first channel to be overlapped at least a portion of the first region;
- a third dielectric between the first selection gate and substrate;
- a fourth dielectric between the first non-volatile storage and first selection gate;
- a second selection gate over the second channel to be overlapped at least a portion of the third region;
- a fifth dielectric between the second selection gate and the substrate;
- a sixth dielectric between the second non-volatile storage and the second selection gate;
- a control plate over the first and second non-volatile storage, the control plate built in a single body;
- and
- a seventh dielectric between the control plate and the non-volatile storage.
14 more elements
A memory device comprising:
- a plurality of memory cells in first and second directions to form an array of memory cells, the memory device having at least one operating mode for at least one of programming, erasing and reading of the memory cells,
- each memory cell having a first transistor with a control gate and a storage gate and a second transistor having a selection gate, wherein a pair of adjacent memory cells commonly share a plate line as the control gate of the first transistor, wherein the first transistor of each memory cell further includes first and second electrodes and the second transistor of each memory cell further includes first and second electrodes, and wherein the second electrode of the first transistor is commonly coupled to the first electrode of the second transistor.
Dependencies are inferred from the claim text.