Magnetic random access memory

A magnetic random access memory comprising:

• a diode;
• a word line electrically coupled to the diode;
• a connection layer electrically coupled to the diode;
• and
• a plurality of connection pairs each connection pair comprising a resistance transfer device and a bit line electrically coupled to the resistance transfer device,
• wherein a first one of the plurality of connection pairs is formed on the connection layer, and
• wherein the bit line of a second one of the plurality of connection pairs is perpendicular to the bit line of the first one of the plurality of connection pairs.

A magnetic random access memory comprising:

• a diode;
• a first word line electrically coupled to the diode;
• a second word line electrically coupled to an external power supply;
• a first connection layer electrically coupled to the diode;
• a first resistance transfer device formed on the first connection layer above the first word line;
• a second resistance transfer device formed on the first connection layer above the second word line;
• and
• a bit line electrically coupled to the first and second resistance transfer devices.

A magnetic random access memory comprising:

• a diode;
• a first word line electrically coupled to the diode;
• a first connection layer electrically coupled to the diode;
• a first resistance transfer device formed on the first connection layer above the first word line;
• a bit line electrically coupled to the first resistance transfer device;
• a second resistance transfer device formed on the bit line above the first resistance, transfer device;
• a second connection layer electrically coupled to the first connection layer and the second resistance transfer device;
• and
• a second word line formed above the second resistance transfer device.

A magnetic random access memory comprising:

• a diode;
• a first word line electrically coupled to the diode;
• a first connection layer electrically coupled to the diode;
• a first resistance transfer device formed on the first connection layer above the first word line;
• a first bit line electrically coupled to the first resistance transfer device;
• a second connection layer electrically coupled to the first bit line;
• a second word line formed between the second connection layer and the first bit line, and above the first resistance transfer device,
• a second resistance transfer device formed above the second word line on the second connection layer;
• and
• a second bit line electrically coupled to the second resistance transfer device.