Semiconductor integrated circuit device with reduced coupling noise
AssigneesRenesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
InventorsNoriyoshi Watanabe, Kazutomo Ogura, Kiyotada Funane
Life of this patent
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Abstract
To a first signal line to which a signal with a comparable small amplitude against the power supply voltage is transmitted at a first timing, a second signal line to which a voltage maintained at a constant is transmitted at the first timing is laid out on the same wiring layer as that of the first signal line adjacently to each other. Thereby, the invention reduces the coupling noises without impairing a high density of the signal wirings, and provides a semiconductor integrated circuit device with a memory circuit that realizes a high integration, low power consumption, and high speed.
Claims16
A semiconductor integrated circuit device comprising:
- a first signal line;
- a second signal line maintained at a specific voltage, at a first timing that a signal with a small amplitude in comparison with a signal amplitude corresponding to a power supply voltage and a ground potential of a circuit is transmitted to the first signal line;
- and
- a third signal line in which a signal change is generated between the power supply voltage and the ground potential of the circuit, in correspondence with the first timing,
- wherein the first signal line and the second signal line are laid out on an identical wiring layer adjacently to each other, and
- wherein the third signal line is formed on a wiring layer different from that on which the first and second signal lines are formed.
A semiconductor integrated circuit device comprising:
- a plurality of word lines and a plurality of complementary bit line pairs;
- a plurality of static type memory cells provided on intersections of the plurality of word lines and plurality of complementary bit line pairs;
- a first selection switch circuit that connects a complementary bit line pair to a complementary signal line pair for writing,
- a second selection switch circuit that connects the complementary bit line pair to a complementary signal line pair for reading,
- a sense amplifier including a latch circuit, of which input and output are coupled to the complementary signal line pair for reading and which is activated by an operational timing signal;
- a specific signal line to which a voltage maintained at a constant is transmitted during an amplifying operation of the sense amplifier, from when information stored in the memory cells are transmitted to the complementary signal line pair for reading through the second selection switch circuit;
- and
- a memory circuit in which the complementary signal line pair for reading and the specific signal line are laid out on an identical wiring layer adjacently to each other.
A semiconductor integrated circuit device comprising:
- a first signal line;
- a second signal line maintained at a specific voltage, at a first timing that a signal with a small amplitude in comparison with a signal amplitude corresponding to a power supply voltage and a ground potential of a circuit is transmitted to the first signal line;
- and
- a third signal line in which a signal change is generated between the power supply voltage and the ground potential of the circuit, in correspondence with the first timing,
- wherein the first signal line and the second signal line are laid out on an identical wiring layer adjacently to each other,
- wherein the third signal line is formed on a wiring layer different from that on which the first and second signal lines are formed, and
- wherein the first, second, and third signal lines each include parts extended in parallel to each other.
A semiconductor integrated circuit device comprising:
- a first wiring to which a signal is transmitted;
- a second wiring to which a power supply voltage or a ground potential of a circuit is supplied;
- and
- a third wiring to which a signal is transmitted, in which, at a first timing that a signal with a small amplitude in comparison with a signal amplitude corresponding to the power supply voltage and the ground potential of the circuit is transmitted to the first wiring, a signal change with a larger amplitude than the small amplitude is generated between the power supply voltage and the ground potential of the circuit,
- wherein the first wiring and the second wiring are laid out on an identical wiring layer adjacently to each other,
- wherein the third wiring is formed on a wiring layer different from that on which the first and second wirings are formed, and
- wherein the first, second, and third wirings each include parts extended in parallel to each other.
Dependencies are inferred from the claim text.