Method and apparatus for reducing substrate bias voltage drop

A processor system comprising:

• a processor;
• a memory device in electrical communication with said processor;
• at least one of said memory device and said processor comprising:
• a semiconductor substrate;
• at least one electrical element fabricated on an upper side of said substrate;
• a plurality of bias voltage distribution regions fabricated over said upper side of said substrate for receiving a bias voltage and providing said bias voltage to said substrate;
• and
• an electrically conductive unbiased layer provided on a back side of said substrate, said layer being adapted to receive an electric charge related to unwanted voltages and electrical noise from a first region of said substrate and return an electric charge to a second different region of said substrate to maintain a uniform bias voltage throughout the substrate.

A semiconductor device comprising:

• a semiconductor substrate;
• at least one electrical element fabricated on said substrate;
• and
• an electrically conductive unbiased layer provided on a back side of said substrate, said conductive layer forming an electrical path for removing unwanted voltages and electrical noise from said substrate at a first region thereof and returning said unwanted voltages and electrical noise to said substrate at a second different region thereof to maintain a uniform bias voltage throughout the substrate.

A semiconductor device comprising:

• a semiconductor substrate;
• at least one electrical element fabricated on an upper side of said substrate;
• a plurality of bias voltage distribution regions fabricated over said upper side of said substrate for receiving a bias voltage and providing said bias voltage to at least some portion of said substrate;
• and
• an electrically conductive unbiased layer provided on a backside of said substrate, said conductive layer forming an electrical path thereby equalizing unwanted voltages and electrical noise on said substrate between a first region of said substrate and a second different region of said substrate to maintain a uniform bias voltage throughout the substrate.

A processor system comprising:

• a processor;
• a memory device in electrical communication with said processor;
• at least one of said memory device and said processor comprising:
• a semiconductor substrate;
• at least one electrical element fabricated on an upper side of said substrate;
• a plurality of bias voltage distribution regions fabricated over said upper side of said substrate for receiving a bias voltage and providing said bias voltage to said substrate, said bias voltage distribution regions including an electrically conductive plug and a metallization layer;
• and
• an electrically conductive unbiased layer provided on a back side of said substrate for transferring unwanted voltages and electrical noise across said substrate to maintain a uniform bias voltage throughout the substrate.

A semiconductor device comprising:

• a semiconductor substrate;
• at least one electrical element fabricated on an upper side of said substrate;
• a plurality of bias voltage distribution regions fabricated over said upper side of said substrate for receiving a bias voltage and providing said bias voltage to at least some portion of said substrate, said bias voltage distribution regions including an electrically conductive plug and a metallization layer;
• and
• an electrically conductive unbiased layer provided on a backside of said substrate, said conductive unbiased layer forming an electrical path between a first region of said substrate and a second region of said substrate for removing unwanted voltages and electrical noise from said substrate to maintain a uniform bias voltage throughout the substrate.