PLL circuit, data detection circuit and disk apparatus

A PLL circuit for generating a clock signal from an input analog signal, comprising:

• an A/D converter for sampling the input analog signal at a fixed clock rate to produce a digital signal;
• an interpolator for adjusting the phase of the digital signal;
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive data values successively outputted from said interpolator and outputting pattern string identification information which indicates an identification result;
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said interpolator based on the pattern string identification information and the output of said interpolator;
• and
• an interpolation amount calculator for controlling the phase adjustment amount of said interpolator based on the phase difference information, wherein said interpolator, said pattern string detector, said phase difference generator, and said interpolation amount calculator are connected in a loop.

A data detection circuit, comprising:

• a PLL circuit including;
• an A/D converter for sampling the input analog signal to produce a digital signal,
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive sample values successively outputted from said A/D converter and outputting pattern string identification information which indicates an identification result,
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said A/D converter based on the pattern string identification information and the output of said A/D converter,
• a clock signal generator for generating a clock signal from the phase difference information to control the sampling timing of said A/D converter;
• and
• a pulse formation circuit for identifying information within the output signal of said A/D converter in synchronism with the clock signal generated by said PLL circuit or the clock signal of the fixed clock, wherein said A/D converter, said pattern string detector, said phase difference generator, and said clock signal generator are connected in a loop.

A data detection circuit, comprising:

• a PLL circuit including:
• an A/D converter for sampling the input analog signal at a fixed clock rate to produce a digital signal,
• an interpolator for adjusting the phase of the digital signal,
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive data values successively outputted from said interpolator and outputting pattern string identification information which indicates an identification result,
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said interpolator based on the pattern string identification information and the output of said interpolator,
• an interpolation amount calculator for controlling the phase adjustment amount of said interpolator based on the phase difference information;
• and
• a pulse formation circuit for identifying information within the output signal of said A/D converter in synchronism with the clock signal generated by said PLL circuit or the clock signal of the fixed clock, wherein said interpolator, said pattern string detector, said phase difference generator, and said interpolation amount calculator are connected in a loop.

A magnetic disk apparatus, comprising:

• magnetic reading means for magnetically reading data from a magnetic disk and outputting the read data as an analog signal;
• and
• a data detection circuit including:
• a PLL circuit which in turn includes:
• an A/D converter for sampling the analog signal from said magnetic reading means to produce a digital signal,
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive sample values successively outputted from said A/D converter and outputting pattern string identification information which indicates an identification result,
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said A/D converter based on the pattern string identification information and the output of said A/D converter, and
• a clock signal generator for generating a clock signal from the phase difference information to control the sampling timing of said A/D converter, and
• a pulse formation circuit for identifying information within the output signal of said A/D converter in synchronism with the clock signal generated by said PLL circuit or the clock signal of the fixed clock, wherein said A/D converter, said pattern string detector, said phase difference generator, and said clock signal generator are connected in a loop.

A magnetic disk apparatus, comprising:

• magnetic reading means for magnetically reading data from a magnetic disk and outputting the read data as an analog signal;
• and
• a data detection circuit including:
• a PLL circuit which in turn includes:
• an A/D converter for sampling the analog signal from said magnetic reading means at a fixed clock rate to produce a digital signal,
• an interpolator for adjusting the phase of the digital signal,
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive data values successively outputted from said interpolator and outputting pattern string identification information which indicates an identification result,
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said interpolator based on the pattern string identification information and the output of said interpolator,
• an interpolation amount calculator for controlling the phase adjustment amount of said interpolator based on the phase difference information, and
• a pulse formation circuit for identifying information within the output signal of said A/D converter in synchronism with the clock signal generated by said PLL circuit or the clock signal of the fixed clock, wherein said interpolator, said pattern string detector, said phase difference generator, and said interpolation amount calculator are connected in a loop.

An optical disk apparatus, comprising:

• optical reading means for optically reading data from an optical disk and outputting the read data as an analog signal;
• and
• a data detection circuit including:
• a PLL circuit which in turn includes an A/D converter for sampling the analog signal from said optical reading means to produce a digital signal,
• an interpolator for adjusting the phase of the digital signal,
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive data values successively outputted from said interpolator and outputting pattern string identification information which indicates an identification result,
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said interpolator based on the pattern string identification information and the output of said interpolator,
• an interpolation amount calculator for controlling the phase adjustment amount of said interpolator based on the phase difference information, and
• a pulse formation circuit for identifying information within the output signal of said A/D converter in synchronism with the clock signal generated by said PLL circuit or the clock signal of the fixed clock, wherein said interpolator, said pattern string detector, said phase difference generator, and said interpolation amount calculator are connected in a loop.

An optical disk apparatus, comprising:

• optical reading means for optically reading data from an optical disk and outputting the read data as an analog signal;
• and
• a data detection circuit including;
• a PLL circuit which in turn includes an A/D converter for sampling the analog signal from said optical reading means at a fixed clock rate to produce a digital signal,
• an interpolator for adjusting the phase of the digital signal,
• a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive data values successively outputted from said interpolator and outputting pattern string identification information which indicates an identification result,
• a phase difference generator for outputting phase difference information which indicates a phase error of the output of said interpolator based on the pattern string identification information and the output of said interpolator,
• an interpolation amount calculator for controlling the phase adjustment amount of said interpolator based on the phase difference information, and
• a pulse formation circuit for identifying information within the output signal of said MD converter in synchronism with the clock signal generated by said PLL circuit or the clock signal of the fixed clock, wherein said interpolator, said pattern string detector, said phase difference generator, and said interpolation amount calculator are connected in a loop.