Apparatus and method for implementing a unified clock recovery system

A method for performing a unified clock recovery procedure, comprising the steps of:

• generating an analog-source reference signal based upon analog-source data by utilizing an analog frontend module;
• generating a digital-source reference signal based upon digital-source data by utilizing a digital frontend module;
• selecting between one of said analog-source reference signal and said digital-source reference signal with a switch module to thereby produce a selected input reference signal;
• utilizing a backend clock recovery module to compare said selected input reference signal with an output reference signal in order to generate a timing error;
• and
• adjusting a local clock with said backend clock recovery module to thereby compensate for said timing error.

A computer-readable medium comprising program instructions for performing a unified clock recovery procedure by performing the steps of:

• generating an analog-source reference signal based upon analog-source data by utilizing an analog frontend module;
• generating a digital-source reference signal based upon digital-source data by utilizing a digital frontend module;
• selecting between one of said analog-source reference signal and said digital-source reference signal with a switch module to thereby produce a selected input reference signal;
• utilizing a backend clock recovery module to compare said selected input reference signal with an output reference signal in order to generate a timing error;
• and
• adjusting a local clock with said backend clock recovery module to thereby compensate for said timing error.

A system for performing a unified clock recovery procedure, comprising:

• means for generating an analog-source reference signal based upon analog-source data;
• means for generating a digital-source reference signal based upon digital-source data;
• means for selecting between one of said analog-source reference signal and said digital-source reference signal to thereby produce a selected input reference signal;
• means for comparing said selected input reference signal with an output reference signal in order to generate a timing error;
• and
• means for adjusting a local clock to compensate for said timing error.

A system for performing a unified clock recovery procedure, comprising:

• an analog frontend module configured to generate an analog-source reference signal;
• a digital frontend module configured to generate a digital-source reference signal;
• a switch module for selecting between said analog-source reference signal and said digital-source reference signal to thereby produce a selected input reference signal;
• and
• a backend clock recovery module configured to utilize said selected input reference signal for determining an output timing error, said backend clock recovery module then adjusting a local clock to compensate for said output timing error.