Vector instruction set
Assignee3Dlabs Inc., Ltd.
InventorDavid Robert Baldwin
Life of this patent
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Abstract
A graphics accelerator architecture in which instructing on a data stream which includes a mixture of scalars and short vectors (i.e. 2-, 3- or 4-vectors) are defined with an argument in the opcode which specifies the data type(s) being manipulated. The sequencer expands each of these opcodes on the fly to produce an appropriate series of instructions for the scalar processor to execute. This is particularly advantageous with the limited set of vector lengths handled in rendering operations.
Claims16
A graphics processing method, comprising the steps of, in a programmable graphics processing stage:
- expanding instructions on the fly using instructions which include both a vector length and an opcode to derive a sequence of one to four scalar operations;
- and
- pipelining execution of said scalar operations in a scalar ALU.
A graphics processing method, comprising the steps of:
- decoding a stream of instructions in which scalar instructions are mixed with vector instructions of no more than four-component vectors;
- expanding respective ones of said vector instructions using instructions which include both a vector length and an opcode into no more than four scalar instructions;
- and
- executing said scalar instructions in one or more scalar processors.
A graphics processor, comprising:
- a programmable graphics computational unit;
- and
- stored program instructions which direct said unit to operate on a data stream which can contain a mixture of scalar and short-vector data;
- wherein said stored instructions include both scalar instructions and also short vector instructions which each specify the number of short vector components to be operated on and also include an opcode;
- wherein said unit includes sequencing logic which expands said instructions, to thereby derive a sequence of no more than four scalar instructions from each said short vector instruction;
- and
- wherein said unit also includes at least one scalar processor which executes said scalar instructions but does not see said short vector instructions.
Dependencies are inferred from the claim text.