Single-chip massively parallel analog-to-digital conversion

A circuit comprising:

• an input terminal coupled to receive an analog input signal;
• and
• a two dimensional array of ADC cells, each ADC cell including a sample-and-hold circuit coupled to an A/D converter, said array of ADC cells being addressed by a plurality of access signals,
• wherein said plurality of access signals selects each sample-and-hold circuit in said array of ADC cells in sequence to cause said sample-and-hold circuits to sample said input analog signal at a plurality of sampling times and store a plurality of analog samples, and said A/D converters in said array of ADC cells convert said plurality of analog samples in parallel to generate digital values representative of said analog samples.

A circuit comprising:

• an input terminal coupled to receive an analog input signal;
• a plurality of analog shift registers, an input terminal of each of said plurality of analog shift registers coupled to said input terminal;
• and
• a plurality of analog-to-digital (A/D) converters, each of said plurality of A/D converters having an input terminal and an output terminal, said input terminal being coupled to an output terminal of a corresponding one of said plurality of analog shift registers,
• wherein said plurality of analog shift registers and said plurality of A/D converters are arranged in a two-dimensional array of ADC cells, each ADC cell including one of said plurality of analog shift registers coupled to one of said plurality of A/D converters, each ADC cell in said two-dimensional array of ADC cells being addressed by a row access signal and a column access signal;
• and
• wherein said plurality of analog shift registers sample said analog input signal sequentially, storing a plurality of analog samples at each of said plurality of analog shift registers;
• and said plurality of A/D converters convert said plurality of analog samples in parallel to generate digital values at said output terminal representative of said analog samples.

A method for performing analog-to-digital conversion comprising:

• providing a two-dimensional array of ADC cells, each ADC cell including a sample-and-hold circuit coupled to an A/D converter and being addressed by a row access signal and a column access signal;
• receiving an analog input signals to be converted into a digital value;
• sampling said analog input signal using said two dimensional array of ADC cells, said analog input signal being sampled sequentially at a plurality of sampling times to generate a plurality of analog samples, each analog sample being stored at a respective one of said sample-and-hold circuit in a respective ADC cell;
• coupling each of said plurality of analog samples to a corresponding input terminal of a respective one of said A/D converters in said two-dimensional array of ADC cells;
• and
• converting said plurality of analog samples to digital values at each of said A/D converters in said two-dimensional array of ADC cells.