Electrically and optically symmetrical analog-to-digital converter for digital pixel sensors

An analog-to-digital (A/D) converter circuit comprising:

• a comparator having a first input terminal coupled to receive a first signal having a plurality of levels, a second input terminal coupled to receive said plurality of analog input signals, and a third input terminal for receiving a plurality of input select signals, said comparator including a multiplexor coupling said plurality of analog input signals to a plurality of corresponding input signal paths, said multiplexor selecting one of said plurality of input signal paths based on said plurality of input select signals;
• and
• a latch having a first input terminal coupled to receive an output signal of said comparator, said latch having a data input terminal coupled to receive a series of binary signals, an output signal of said comparator controlling when said latch provides an output signal corresponding to a binary signal applied to said data input terminal,
• wherein said comparator compares said first signal with a selected one of said plurality of analog input signals to generate said output signal, and said latch provides one or more bits of an N-bit digital code representing said selected one of said plurality of analog input signals applied to said second input terminal of said comparator;
• and
• wherein said comparator comprises a differential pair and a buffer, said buffer having an input terminal coupled to an output terminal of said differential pair and generating said output signal of said comparator, said differential pair comprising:
• a first transistor having a control terminal coupled to receive said first signal, a first current handling terminal coupled to a current mirror, and a second current handling terminal coupled to a current source;
• and
• a first node coupling said plurality of input signal paths to said current mirror, each of said plurality of input signal paths including a second transistor and a third transistor connected in series between said first node and said current source, said second transistor having a control terminal coupled to a respective one of said input select signal, and said third transistor having a control terminal coupled to a respective one of said plurality of analog input signals, said first node being said output terminal of said differential pair,
• wherein said plurality of input select signals selectively enable one of said plurality of input signal paths.

A method for performing analog-to-digital conversion comprising:

• receiving a first analog signal having a plurality of levels;
• receiving a plurality of analog input signals each to be converted into a digital value;
• coupling said plurality of analog input signals to a corresponding plurality of differential pairs in a comparator;
• selecting one of said plurality of differential pairs based on a plurality of input select signals;
• comparing said first analog signal to a selected analog input signal associated with said selected one of said plurality of input signal paths, and outputting a comparison result;
• receiving a series of binary signals;
• and
• applying said comparison result to a first input of a latch, and applying said series of binary signals to a data input of said latch, a logic level of said comparison result controlling when said latch provides an output signal corresponding to a binary signal applied to said data input,
• wherein said latch provides one or more bits of an N-bit digital code representing at least one of said analog input signals.

A method for performing analog-to-digital conversion comprising:

• receiving a first reference signal corresponding to a plurality of decrementing digital count values;
• receiving a plurality of analog input signals each to be converted into a digital value;
• coupling said plurality of analog input signals to a corresponding plurality of differential pairs in a comparator;
• selecting one of said plurality of differential pairs based on a plurality of input select signals;
• comparing said first reference signal to a selected analog input signal associated with said selected one of said plurality of input signal paths, and outputting a comparison result;
• and
• applying said comparison result to a buffer,
• wherein said buffer provides one or more bits of an N-bit digital code representing at least one of said analog input signals.