Method and system for implementing a sigma delta analog-to-digital converter
AssigneeGlobespanVirata, Inc.
InventorsAlper Tunga Erdogan, Chung-Li Lu, Bijit Halder
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Abstract
An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.
Claims20
An analog-to-digital converter comprising:
- a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal;
- and
- a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least:
- a first decimator comprising a first integrator filter;
- a first downsampling block and a first differentiator;
- and
- a second decimator comprising a second integrator filter;
- a second downsampling block and a second differentiator.
A method for implementing an analog-to-digital converter, the method comprising the steps of:
- receiving a plurality of inputs by a first filter and a second filter;
- generating a combined signal in response to the plurality of inputs;
- receiving the combined signal;
- generating a digital sigma-delta output in response to the combined signal, wherein the digital sigma-delta output is generated by at least:
- a first decimator comprising a first integrator filter;
- a first downsampling block and a first differentiator;
- and
- a second decimator comprising a second integrator filter;
- a second downsampling block and a second differentiator.
Dependencies are inferred from the claim text.