Digital decimation filter
AssigneeMicrochip Technology Incorporated
InventorsVincent Quiquempoix, Gabriele Bellini, Jerry Collings
Life of this patent
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Abstract
A digital decimation filter with programmable frequency notches is disclosed. The digital decimation filter performs integration, differentiation, and scaling to produce a filtered output signal. The differentiation is preformed by a programmable counter. The filter has a control unit that controls the behavior of the filter. The control unit has registers to contain ther values of the frequency notches of the filter. The control unit activates the differentiator based on the value of the frequency notches in order to achieve filtration. The scaling unit uses a register, a bit shifter, and an adder to minimize complexity. The digital decimation filter provides high rejection with low complexity.
Claims18
A digital decimation filter, including:
- a programmable power supply for supplying power to electronic circuits of electronic equipment;
- a integrator adapted to receive an input signal, the input signal including one or more frequency components;
- a differentiator coupled to the integrator, the differentiator including a programmable counter;
- a scaling unit coupled to the differentiator, the scaling unit adapted to produce an output signal;
- and
- a control unit coupled to the integrator, the differentiator, and the scaling unit, the control unit adapted to store one or more programmable frequency notches, wherein the control unit activates the programmable counter such that the output signal is a filtered version of the input signal wherein the frequency components corresponding to the programmable frequency notches are attenuated.
The method of filtering a signal, including:
- integrating the signal to produce an integrated signal;
- selectively differentiating the integrated signal using a programmable counter to produce a differentiated signal, wherein the integrated signal is differentiated according to one or more programmable frequency notches;
- scaling the differentiated signal to achieve a desired gain for a DC signal;
- and
- resampling the integrated signal at a frequency lower than a clock frequency.
A delta-sigma analog-to-digital converter including:
- a digital decimation filter, the digital decimation filter adapted to receive an input and produce an output;
- wherein the digital decimation filter includes an integrator and a differentiator coupled together;
- wherein the differentiator includes a programmable counter;
- a scaling unit coupled to the differentiator, the scaling unit operable to produce an output signal, wherein the output signal is a scaled version of the input;
- and
- wherein the programmable counter is adapted to selectively differentiate an input signal according to one or more programmable frequency notches.
A signal processing apparatus, including:
- a integrator adapted to receive an input signal, the input signal including one or more frequency components;
- a differentiator coupled to the integrator, the differentiator including a programmable counter;
- a scaling unit coupled to the differentiator, the scaling unit adapted to produce an output signal;
- and
- a control unit coupled to the integrator, the differentiator, and the scaling unit, the control unit adapted to store one or more programmable frequency notches, wherein the control unit activates the programmable counter such that the output signal is a filtered version of the input signal wherein the frequency components corresponding to the programmable frequency notches are attenuated.
Dependencies are inferred from the claim text.