Addressing device for selecting regular and redundant elements

An addressing device for selecting an element from one of a set of N≦2K regular elements and a set of R<N redundant elements depending on binary values of address bits of a K-bit input address, the addressing device comprising:

• a 1-out-of-N decoder having K address inputs receiving the address bits and N outputs coupled to the N regular elements;
• R bypass circuits each coupled to precisely one of the redundant elements, said R bypass circuits each coupled to said 1-out-of N decoder and each containing:
• a sensitization circuit for setting a respective bypass circuit into an active state;
• a reference bit transmitter having programmable links and supplying K reference bits individually assigned to the K address bits and values of the K reference bits being programmable by programming said programmable links, said programmable links selected from the group consisting of fuses and anti-fuses, said reference bit transmitter coupled to said sensitization circuit;
• a comparison device connected to said reference bit transmitter and deriving K comparison bits from the reference bits, said comparison device comparing the comparison bits with the address bits and supplying a hit information item if the address bits correspond to a bit combination unambiguously related to the comparison bits;
• and
• a control circuit receiving the hit information item, upon receiving the hit information item said control circuit supplying a selection signal for switching off said 1-out-of-N decoder and addresses an associated redundant element if said respective bypass circuit is in the active state;
• said sensitization circuit receiving M≦K preselected reference bits from said reference bit transmitter of said respective bypass circuit and sets said respective bypass circuit into the active state if binary values of the M preselected reference bits received differ from a chosen bit combination.