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US 6,788,156 B2Granted
Adaptive variable frequency clock system for high performance low power microprocessors
AssigneeIntel Corporation
InventorsSimon M. Tam, Stefan Rusu
Life of this patent
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Abstract
A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
Claims10
A method comprising:
- switching a source for a core clock from a first clock generator to an adjustable clock generator;
- monitoring operation of core circuitry;
- determining whether to adjust from a present operating point for said core circuitry;
- toggling said adjustable clock generator to a new setting if said determination indicates an operating point adjustment is needed;
- outputting a clock signal having a new frequency from said adjustable clock generator to said core clock;
- syncing said adjustable clock generator to said first clock generator before said switching;
- and
- enabling control logic to shift an operating point for said core circuitry, wherein said present operating point is shifted by adjusting to a new clock frequency and a new processor supply voltage.
5 more elements
A method comprising:
- switching a source for a core clock from a first clock generator to an adjustable clock generator;
- monitoring operation of core circuitry;
- determining whether to adjust from a present operating point for said core circuitry;
- toggling said adjustable clock generator to a new setting if said determination indicates an operating point adjustment is needed;
- outputting a clock signal having a new frequency from said adjustable clock generator to said core clock;
- syncing said adjustable clock generator to said first clock generator before said switching;
- enabling control logic to shift an operating point for said core circuitry;
- and
- selecting a new operating point for said core circuitry, wherein said selecting further comprises generating a set of control bits to indicate a new frequency setting and a new voltage setting.
6 more elements
An apparatus comprising:
- clock switching logic coupled to provide one of its inputted clocks as a core clock signal to core circuitry;
- a first clock generator coupled to input a first clock signal to said clock switching logic;
- an adjustable clock generator coupled to input an adjustable clock signal to said clock switching logic to adjust said frequency without stopping operation of said core circuitry, wherein said adjustable clock generator is a coupled oscillator clock generator comprising:
- a digital-to-analog converter coupled to said control logic, said digital-to-analog converter to receive frequency offset settings from said control logic;
- and
- a voltage controlled oscillator coupled to said digital-to-analog converter, said
- voltage control oscillator to generate said adjustable clock signal,
- control logic coupled to said clock switching logic, said control logic to determine which of said inputted clocks at said clock switching logic is selected for output as said core clock signal and wherein said control logic determines frequency steps and adjustments for said adjustable clock generator.
5 more elements
Dependencies are inferred from the claim text.