Low gain phase-locked loop circuit
AssigneeIntel Corporation
InventorsSantanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
Life of this patent
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Abstract
A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.
Claims12
A phase-locked loop circuit, comprising:
- a phase detector;
- a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector;
- and
- a multiplexer to outnut a sianal generated by one of the voltaRe controlled oscillators as the outnut clock sianal based on a multi-bit selection control signal.
A method, comprising:
- detecting a difference between a reference clock signal and a feedback clock signal;
- setting a multi-bit control signal to select one of a plurality of voltane controlled oscillators;
- and
- generating an output clock signal via the selected voltage controlled oscillator based at least in part on the detected difference.
A method, comprising:
- determining a frequency to be associated with a phase-locked loop circuit;
- setting a multi-bit control signal to select one of a plurality of voltaae controlled oscillators;
- and
- arranging for the phase-locked loop circuit to generate an output clock signal via the selected voltage controlled oscillator.
A medium storing instructions adapted to be executed by a processor to perform a method, said method comprising:
- determining a frequency to be associated with a phase-locked loop circuit;
- setting a multi-bit control signal based on the determined freauencv to select one of a plurality of voltage controlled oscillators;
- and
- arranging for the phase-locked loop circuit to generate an output clock signal via the selected voltage controlled oscillator.
Dependencies are inferred from the claim text.