Cascode stage for an operational amplifier

An apparatus comprising a cascode stage and an input stage, the cascode stage comprising:

• a first current source that is coupled to a first node;
• a second current source that is coupled to a second node;
• a first transistor that is coupled between a first power supply and a fifth node, wherein the first transistor is biased by a third node;
• a second transistor that is coupled between the first power supply and a sixth node, wherein the second transistor is biased by the third node;
• a third transistor that is coupled between the third node and the fifth node wherein the third transistor is biased by a second power supply;
• a fourth transistor that is coupled between a fourth node and the sixth node, wherein the fourth transistor is biased by the second power supply;
• a fifth transistor that is coupled between the first node and the third node, wherein the fifth transistor is biased by a bias signal;
• and
• a sixth transistor that is coupled between the second node and the fourth node, wherein the sixth transistor is biased by the bias signal, such that the fourth node operates as a high impedance node that is responsive to current signals that are provided to the first and second nodes, respectively;
• the input stage comprising:
• a differential pair that includes a seventh transistor and an eighth transistor that share a common node that is coupled to a third current source that provides a third current, wherein the seventh transistor is arranged to provide a first portion of the third current to the first node, and the eighth transistor is arranged to provide a second portion of the third current to the second node such that the first and second portions of the third current are determined by the differential input signal, the input stage being arranged to receive a differential input signal and provide the current signals to the first and second nodes, respectively;
• and
• level shifter circuits that are arranged to change the DC level associated with the differential input signal such that the seventh and eighth transistors are biased in active operation.

An operational amplifier, comprising:

• a cascode stage comprising:
• a first current source than is coupled to a first node;
• a second current source that is coupled to a second node;
• a first transistor that is coupled between a first power supply and a fifth node, wherein the first transistor is biased by a third node,
• a second transistor that is coupled between the first power supply and a sixth node, wherein the second transistor is biased by the third node;
• a third transistor that is coupled between the third node and the fifth node, wherein the third transistor is biased by a second power supply;
• a fourth transistor that is coupled between a fourth node and the sixth node, wherein the fourth transistor is biased by the second power supply;
• a fifth transistor that is coupled between the first node and the third node, wherein the fifth transistor is biased by a bias signal;
• and
• a sixth transistor that is coupled between the second node and the fourth node,
• wherein the sixth transistor is biased by the bias signal, such that the fourth node operates as the high impedance node;
• an input stage that is arranged to provide a first current to the first node and a second current to the second node in response to a differential input signal the input stage comprising:
• a third current source that is coupled to a common node;
• a seventh transistor that is coupled between the first node and the common node,
• wherein the seven transistor is responsive to a first portion of the differential input signal;
• and
• an eighth transistor that is coupled between the second node and the common node, wherein the eighth transistor is responsive to a second portion of the differential input signal;
• an output stage that is arranged to provide an output signal in response to a high gain signal, wherein the input stage, the cascode stage, and the output stage are arranged to cooperate with one another such that the differential input signal is amplified to provide the output signal, the output stage comprising a ninth transistor and a resistor, wherein the ninth transistor and the resistor are configured to operate as a gain stage that is responsive to the high gain signal.

An operational amplifier, comprising:

• a cascode stage comprising:
• a first current source that is coupled to a first node;
• a second current source that is coupled to a second node;
• a first transistor that is coupled between a first power supply and a fifth node,
• wherein the first transistor is biased by a third node;
• a second transistor that is coupled between the first power supply and a sixth node, wherein the second transistor is biased by the third node;
• a third transistor that is coupled between the third node and the fifth node,
• wherein the third transistor is biased by a second power supply;
• a fourth transistor that is coupled between a fourth node and the sixth node,
• wherein the fourth transistor is biased by the second power supply;
• a fifth transistor that is coupled between the first node and the third node, wherein the fifth transistor is biased by a bias signal;
• and
• a sixth transistor that is coupled between the second node and the fourth node,
• wherein the sixth transistor is biased by the bias signal, such that the fourth node operates as the high impedance node;
• an input stage that is arranged to provide a first current to the first node and a second current to the second node in response to a differential input signal the input stage further comprising:
• a third current source that is coupled to a common node;
• a seventh transistor that is coupled between the first node and the common node,
• wherein the seventh transistor is responsive to a first portion of the differential input signal;
• an eighth transistor that is coupled between the second node and the common node, wherein the eighth transistor is responsive to a second portion of the differential input signal;
• and
• level shifter circuits that are arranged to change the DC level associated with the differential input signal such that the seventh and eighth transistors are biased in active operation;
• and
• an output stage that is arranged to provide an output signal in response to a high gain signal, wherein the input stage, the cascode stage, and the output stage are arranged to cooperate with one another such that the differential input sign is amplified to provide the output signal.

An apparatus comprising a cascode stage, the cascode stage comprising:

• a first current source that is coupled between a first node and a first power supply,
• a second current source that is coupled between a second node and a second power supply;
• a first transistor that is coupled between a second power supply and a fifth node, wherein the first transistor is biased by a third node;
• a second transistor that is coupled between the second power supply and a sixth node, wherein the second transistor is biased by the third node;
• a third transistor that is coupled between the third node and the fifth node, wherein the third transistor is biased by a bias signal;
• a fourth transistor that is coupled between a fourth node and the sixth node, wherein the fourth transistor is biased by the bias signal;
• a fifth transistor that is coupled between the fist node and the third node, wherein the fifth transistor is biased by the second power supply;
• a sixth transistor that is coupled between the second node and the fourth node, wherein the sixth transistor is biased by the second power supply such that the fourth node operates as a high impedance node that is responsive to current signals that are provided to the first and second nodes, respectively;
• and
• a ninth transistor and a resistor that are arranged to operate as a gain stage, wherein the gain stage is arranged to receive a high gain signal from the high impedance node such that the gain stage provides an output signal in response to the high gain signal.