Wide common mode differential input amplifier and method

A wide input range amplifier comprising:

• a first stage having first and second inputs, first and second outputs, and first, second and third voltage sources, said first stage accepting input signals having a first common mode voltage range and outputting a first output signal having a second common mode voltage range and being amplified a first amount;
• a second stage having first and second inputs connected to said first and second outputs of said first stage, respectively, said second stage accepting input signals having a common mode voltage in said second range and outputting a second output signal having a third common mode voltage range and being amplified a second amount,
• wherein said first stage comprises a P-type common source pair connected to a first current source and an N-type common source pair connected to a second current source, and first and second differential resistors, and wherein
• said first current source is connected to said first voltage source, said second current source is connected to said second voltage source, a gate of a first transistor of said P-type common source pair being connected to said first input, a gate of a second transistor of said P-type common source pair being connected to said second input, a gate of a first transistor of said N-type common source pair being connected to said first input, a gate of a second transistor of said N-type common source pair being connected to said second input, a drain of said first transistor of said P-type common source pair being connected to said first output, a drain of said second transistor of said P-type common source pair being connected to said second output, a drain of said first transistor of said N-type common source pair being connected to said first output, a drain of said second transistor of said N-type common source pair being connected to said second input, and said pair of load resistors being connected two each other and two said first and second outputs, and said mid-point of said pair of load resistors being connected to said third voltage source.

A wide input range amplifier comprising:

• a first stage having first and second inputs, first and second outputs, and first, second and third voltage sources, said first stage accepting input signals having a first common mode voltage range and outputting a first output signal having a second common mode voltage range and being amplified a first amount;
• a second stage having first and second inputs connected to said first and second outputs of said first stage, respectively, said second stage accepting input signals having a common mode voltage in said second range and outputting a second output signal having a third common mode voltage range and being amplified a second amount,
• wherein said first stage further comprises complementary first and second input pairs, first and second differential resistors, and a first and second pair of cascoded transistors, and wherein
• said first input pair is of a first semi-conductor type and said second input pair is of a second semi-conductor type, and said load resistors are loaded across said first and second outputs as load resistors.

A method of buffering an input signal, said method comprising:

• providing a first amplifier stage for receiving an input signal having a first voltage range, amplifying said input signal a first amount, and outputting an output signal having a second voltage range being amplified said first amount;
• providing a second amplifier stage for receiving said output signal from said first amplifier stage, amplifying said output signal a second amount, and outputting a differential output signal having a third voltage range being amplified said second amount,
• wherein said providing a first amplifier stage step comprises:
• providing complementary input pairs for receiving said input signal,
• configuring a first input pair of said complementary input pairs to be OFF and a second input pair of said complementary input pairs to be ON, when said input signal is above a first input voltage, and
• configuring said first input pair of said complementary input pairs to be ON and said second input pair of said complementary input pairs to be OFF, when said input signal is below a first input voltage.

A method of buffering an input signal, said method comprising:

• providing a first amplifier stage for receiving an input signal having a first voltage range, amplifying said input signal a first amount, and outputting an output signal having a second voltage range being amplified said first amount;
• providing a second amplifier stage for receiving said output signal from said first amplifier stage, amplifying said output signal a second amount, and outputting a differential output signal having a third voltage range being amplified said second amount,
• wherein said providing a first amplifier stage step further comprises:
• providing a P-type common source pair connected to a first current source and an N-type common source pair connected to a second current source, and first and second differential resistors,
• loading said first and second differential resistors across said output of said first stage amplifier,
• connecting said first current source to a first voltage source,
• connecting said second current source to a second voltage source,
• connecting a gate of a first transistor of said P-type common source pair to said first input,
• connecting a gate of a second transistor of said P-type common source pair to said second input,
• connecting a gate of a first transistor of said N-type common source pair to said first input,
• connecting a gate of a second transistor of said N-type common source pair to said second input,
• connecting a drain of said first transistor of said P-type common source pair to said first output,
• connecting a drain of said second transistor of said P-type common source pair to said second output,
• connecting a drain of said first transistor of said N-type common source pair to said first output,
• connecting a drain of said second transistor of said N-type common source pair to said second input,
• connecting said first and second differential resistors to each other and to said first and second outputs, and
• connecting a mid-point of said first and second differential resistors to a third voltage source.

A method of buffering an input signal, said method comprising:

• providing a first amplifier stage for receiving an input signal having a first voltage range, amplifying said input signal a first amount, and outputting an output signal having a second voltage range being amplified said first amount:
• providing a second amplifier stage for receiving said output signal from said first amplifier stage, amplifying said output signal a second amount, and outputting a differential output signal having a third voltage range being amplified said second amount,
• wherein said providing a first amplifier stage step further comprises:
• providing complementary first and second input pairs, said first input pair is of a first semi-conductor type and said second input pair is of a second semi-conductor type,
• providing first and second differential resistors connected across said output of said first amplifier stage as load resistors, and
• providing a first and second pair of cascoded transistors, said first pair of cascoded transistors cascoded with said second input pair, and said second pair of cascoded transistor cascoded with said first input pair.

A method for receiving a signal, said method comprising the steps of:

• receiving a thick device signal having a first common mode range;
• amplifying said thick device signal a first amount and stepping said thick device signal down to a first thin device signal having a second common mode range;
• and
• amplifying said thin device signal a second amount and outputting a second thin device signal having a third common mode voltage range,
• wherein said step of amplifying said thick device signal includes steps of:
• determining whether said first common mode range is above or below a threshold voltage, and
• amplifying said thick device signal a first amount and stepping said thick device signal down to said first thin device signal based on the determination.

A method for receiving a signal, said method comprising the steps of:

• receiving a thick device signal having a first common mode range;
• amplifying said thick device signal a first amount and stepping said thick device signal down to a first thin device signal having a second common mode range;
• and
• amplifying said thin device signal a second amount and outputting a second thin device signal having a third common mode voltage range,
• wherein said step of amplifying said thin device signal includes a step of adjusting gain of said thin device signal to differential transistors to produce said second thin device signal as a differential output.