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US 6,788,136 B2Granted
Methods and apparatus for amplification in high temperature environments
AssigneeGeneral Electric Company
InventorDonald Thomas McGrath
Life of this patent
Estimating the term…
Abstract
In one aspect, the present invention provides a method for amplifying a signal including generating an input signal and amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.
Claims14
A method for amplifying a signal comprising:
- generating an input signal;
- amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion made operational amplifier to produce an amplified output signal, the operational amplifier including a first NMOS depletion mode amplification stage and a second NMOS depletion mode amplification stage, the first stage and the second stage fabricated on the same silicon carbide substrate, wherein amplifying the input signal comprises chopping the input signal utilizing a first NMOS depletion mode chopping switch responsive to a first chopping signal to produce a first chopped input signal;
- and
- generating at least one opposite node of a resistor of an NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit, the first chopping signal, and the level shifted first chopping signal in response to a clock signal.
1 more element
An operational amplifier circuit comprising:
- a first NMOS depletion mode amplification stage;
- a first NMOS depletion mode chopping switch responsive to a first chopping signal to chop an input signal to said first amplification stage;
- a second NMOS depletion mode chopping switch responsive to a level shifted first chopping signal to chop an output signal from said first amplification stage;
- and
- an NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to a clock signal to generate said first chopping signal and said level shifted first chopping signal across a voltage dropping element.
2 more elements
An operational amplifier circuit comprising:
- a first NMOS depletion mode amplification stage;
- a first NMOS depletion mode chopping switch responsive to a first chopping signal to chop an input signal to said first amplification stage;
- a second NMOS depletion mode chopping switch responsive to a level-shifted first chopping signal to chop an output signal from said first amplification stage;
- and
- and an NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to a clock signal to generate said first chopping signal and said level shifted first chopping signal across a resistor;
- and further wherein said first NMOS depletion mode amplification stage, first NMOS depletion mode chopping switch, second NMOS depletion mode chopping switch, and said NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit are fabricated on the same silicon carbide substrate.
3 more elements
An operational amplifier circuit comprising:
- a first NMOS depletion mode amplification stage having differential inputs and outputs;
- a first NMOS depletion mode chopping switch responsive to a first chopping signal and a second chopping signal to chop a differential input signal to said first amplification stage,
- a second NMOS depletion mode chopping switch responsive to a level-shifted first chopping signal and a level shifted second chopping signal to chop an output signal from said first amplification stage;
- a first NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to a clock signal to generate said first chopping signal and said level shifted first chopping signal across a first resistor;
- a second NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to said clock signal to generate said second chopping signal and said level shifted second chopping signal across a second resistor;
- and
- a clock generator circuit configured to generate said clock signal.
4 more elements
Dependencies are inferred from the claim text.