Terminating pathway for a clock signal

A signal pathway formed on an integrated circuit mounted to a circuit board, the integrated circuit comprising a package and a die, the signal pathway comprising:

• a first integrated circuit signal line extending into the package from a signal-in pad disposed on the surface of the circuit board, the first integrated circuit signal line forming a stub extending at least to an interface of the die and the package;
• and
• a second integrated circuit signal line branching from the first signal line portion at a base of the stub and extending to a signal-out pad;
• whereby clock signals may enter the integrated circuit at the signal-in pad and exit the integrated circuit at the signal-out pad.

A signal pathway for carrying clock signals from a clock driver to a circuit component mounted to a circuit board, the signal pathway having a termination on the circuit board and being configured to minimize signal reflections and signal degradation, the signal pathway comprising:

• a first signal line formed on a circuit board and electrically connected to a clock driver, the first signal line extending to a first terminal;
• a second signal line formed on the circuit board and extending from a second terminal to a termination;
• a third signal line formed in the circuit component, the third signal line extending from a signal in pad electrically connected to the first terminal to a signal out pad electrically connected to the second terminal;
• and
• a stub electrically connected to the second signal line on the circuit component.

An electronic system, comprising:

• a circuit board having an interface;
• a circuit component mounted onto the circuit board interface to electrically couple the circuit component to the circuit board;
• and
• a signal pathway, comprising:
• a first signal line formed on the circuit board and electrically connected to a clock driving means, the first signal line extending to a first terminal;
• a second signal line formed on the circuit board and extending from a second terminal to a termination;
• a third signal line formed on the circuit component, the third signal line extending from a signal in pad electrically coupled to the first terminal at the circuit board interface to a signal out pad electrically coupled to the second terminal at the interface;
• and
• a stub electrically coupled with the third signal line on the circuit component.
• wherein the clock driving means generates clock signals to be carried by the signal pathway to the circuit component and on to the termination.

A method for routing a clock signal to a receiver whereby a waveform of the clock signal has an acceptably low amount of noise at the receiver, the receiver comprising circuit component, the method comprising the steps of:

• providing a signal pathway, comprising:
• a first signal line formed on a circuit board and electrically connected to a clock driver, the first signal line extending to a first terminal;
• a second signal line formed on the circuit board and extending from a second terminal to a termination;
• a third signal line formed on the circuit component mounted to the circuit board, the third signal line extending from a signal in pad electrically coupled with the first terminal to a signal out pad electrically coupled with the second terminal;
• and
• a stub electrically coupled with the third signal line on the circuit component;
• and
• driving the clock signal, by the clock driver, along the signal pathway to the circuit component and on to a termination.