Circuit for variably delaying data

Abstract

A circuit for variably delaying a serial digital data signal delays a parallel data clock rather than the serial digital data signal directly. A delay circuit receives the parallel data clock to provide a delayed parallel data clock, the delay being a function of a control signal. A phase-locked loop receives the delayed parallel data clock to generate a serial data clock in phase with the delayed parallel data clock. A parallel-to-serial converter reads an n-bit parallel digital data signal from a memory using the delayed parallel data clock, and converts the parallel digital data signal to the serial digital data signal using the serial data clock. By changing the control signal continuously, the delay of the delayed parallel data clock and of the serial digital data signal also changes continuously so the serial digital data signal appears to have jitter.

Dependencies are inferred from the claim text.