Semiconductor buffer circuit with a transition delay circuit

A buffer circuit, comprising:

• a transition delay circuit having an input terminal and an output terminal, wherein the transition delay circuit includes:
• a first MOS capacitor having a first terminal and a gate terminal, wherein the first terminal is connected to the input terminal of the transition delay circuit and the gate terminal is connected to the output terminal of the transition delay circuit;
• a second MOS capacitor having a first terminal and a gate terminal, wherein the first terminal of the second MOS capacitor is connected to the input terminal of the transition delay circuit and the gate terminal of the second MOS capacitor is connected to the output terminal of the transition delay circuit, and wherein the second MOS capacitor has a different polarity than the first MOS capacitor;
• and
• a delay circuit having first and second terminals, wherein the first terminal of the delay circuit is connected to the input terminal of the transition delay circuit and the second terminal of the delay circuit is connected to the output terminal of the transition delay circuit;
• and
• an inverter connected to the output terminal of the transition delay circuit.

A device, comprising:

• a buffer circuit, wherein the buffer circuit includes:
• a transition delay circuit having an input terminal and an output terminal, wherein the transition delay circuit includes:
• a first MOS capacitor having a first terminal and a gate terminal, wherein the first terminal is connected to the input terminal of the transition delay circuit and the gate terminal is connected to the output terminal of the transition delay circuit;
• a second MOS capacitor having a first terminal and a gate terminal, wherein the first terminal of the second MOS capacitor is connected to the input terminal of the transition delay circuit and the gate terminal of the second MOS capacitor is connected to the output terminal of the transition delay circuit, and wherein the second MOS capacitor has a different polarity than the first MOS capacitor;
• and
• a delay circuit having first and second terminals, wherein the first terminal of the delay circuit is connected to the input terminal of the transition delay circuit and the second terminal of the delay circuit is connected to the output terminal of the transition delay circuit;
• and
• an inverter connected to the output terminal of the transition delay circuit;
• and
• a functional circuit connected to the buffer circuit.

A system, comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device includes:
• a buffer circuit;
• and
• a functional circuit connected to the buffer circuit, wherein the buffer circuit includes:
• a transition delay circuit having an input terminal and an output terminal, wherein the transition delay circuit includes:
• a first MOS capacitor having a first terminal and a gate terminal, wherein the first terminal is connected to the input terminal of the transition delay circuit and the gate terminal is connected to the output terminal of the transition delay circuit;
• a second MOS capacitor having a first terminal and a gate terminal, wherein the first terminal of the second MOS capacitor is connected to the input terminal of the transition delay circuit and the gate terminal of the second MOS capacitor is connected to the output terminal of the transition delay circuit, and wherein the second MOS capacitor has a different polarity than the first MOS capacitor;
• and
• a delay circuit having first and second terminals, wherein the first terminal of the delay circuit is connected to the input terminal of the transition delay circuit and the second terminal of the delay circuit is connected to the output terminal of the transition delay circuit;
• and
• an inverter connected to the output terminal of the transition delay circuit.

A system, comprising:

• a memory device;
• and
• a processor in communication with the memory device, wherein the processor includes:
• a buffer circuit;
• and
• a functional circuit connected to the buffer circuit, wherein the buffer circuit includes:
• a transition delay circuit having an input terminal and an output terminal, wherein the transition delay circuit includes:
• a first MOS capacitor having a first terminal and a gate terminal, wherein the first terminal is connected to the input terminal of the transition delay circuit and the gate terminal is connected to the output terminal of the transition delay circuit;
• a second MOS capacitor having a first terminal and a gate terminal, wherein the first terminal of the second MOS capacitor is connected to the input terminal of the transition delay circuit and the gate terminal of the second capacitor is connected to the output terminal of the transition delay circuit, and wherein the second MOS capacitor has a different polarity than the first MOS capacitor;
• and
• a delay circuit having first and second terminals, wherein the first terminal of the delay circuit is connected to the input terminal of the transition delay circuit and the second terminal of the delay circuit is connected to the output terminal of the transition delay circuit;
• and
• an inverter connected to the output terminal of the transition delay circuit.

A method for minimizing transition delay differences of a signal, the method comprising:

• applying the signal to a first terminal of a first MOS capacitor and a first terminal of a second MOS capacitor, wherein the second MOS capacitor has a different polarity than the first MOS capacitor;
• delaying the signal;
• and
• applying the delayed signal to a gate terminal of the first MOS capacitor and a gate terminal of the second MOS capacitor.