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US 6,788,123 B2Granted
Unity gain interpolator for delay locked loops
Assigneen Microsystems, Inc.
InventorAninda K. Roy
Life of this patent
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Abstract
A method and apparatus for delaying a clock signal involves a first clock path arranged to propagate a first clock signal; a second clock path arranged to propagate a second clock signal; and an interpolator arranged as a unity gain operational amplifier. An amount of delay between the first and second clock signals is determined by a control voltage potential.
Claims20
A clock signal delay apparatus, comprising:
- a first clock path arranged to propagate a first clock signal;
- a second clock path arranged to propagate a second clock signal, the second clock signal being a delayed version of the first clock signal;
- and
- a first interpolator arranged to output the second clock signal responsive to the first clock signal, wherein an amount of delay between the first clock signal and the second clock signal is determined by a first control voltage potential, and wherein the first interpolator is arranged as a unity gain operational amplifier.
1 more element
A method for delaying a clock signal, comprising:
- transmitting a first clock signal;
- transmitting a second clock signal, the second clock signal being a delayed version of the first clock signal;
- and
- outputting the second clock signal responsive to the first clock signal using a first interpolator arranged as a unity gain operational amplifier, wherein an amount of delay between the first clock signal and the second clock signal is determined by a first control voltage potential.
1 more element
Dependencies are inferred from the claim text.