Clock controlled power-down state
AssigneesUnited Memories, Inc., Sony Corporation
InventorOscar Frederick Jones, Jr.
Life of this patent
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Abstract
A circuit and method reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method can be used for half-cycle latches and full cycle latches in conjunction with alternate power-gated circuitry, even when many stages are cascaded in a pipeline structure. The data state on a single forcing node can be passed through one or more cascaded latch stages as well as through additional circuitry. By forcing latch transmission gates to be conductive during standby mode, multiple stages can be set to a specific state, as determined by an earlier stage being set by a forcing transistor. A clock generation. circuit and method is also provided for controlling transmission gates within the latches.
Claims10
A full cycle latch comprising:
- a forcing transistor having a gate for receiving a control signal and a drain for receiving an input signal;
- a first transmission gate having an input for receiving the input signal, and an output;
- a first latch stage having an input coupled to the output of the first transmission gate and an output;
- a second transmission gate having an input coupled to the output of the first latch stage, and an output:
- a second latch stage having an input coupled to the output of the second transmission gate and an output for providing an output signal;
- and
- means for forcing the first and second transmission gates to be conductive during a standby mode of operation.
Dependencies are inferred from the claim text.