Counter-based duty cycle correction systems and methods

A system providing a symmetrical output clock signal from an asymmetrical input clock signal, the system comprising:

• first counter means for counting a number of counts in a period of the input clock signal;
• register means for storing one-half the number of counts counted by the first counter means;
• second counter means for counting a number of counts following a first edge of the input clock signal;
• comparator means for comparing a value stored in the register means with a value stored in the second counter means and for providing a match output signal to the second counter means whenever a match is detected;
• and
• output clock generator means for providing the first edge on the output clock signal each time the first edge occurs on the input clock signal, and for providing an opposite edge on the output clock signal each time the match output signal from the comparator shows a match.

A method of performing a duty cycle correction on an input clock signal comprising alternating first and second edges, the method comprising:

• counting a first number of counts between successive first edges of the input clock signal;
• dividing the first number and storing a resulting divided number;
• counting a second number of counts following each first edge of the input clock signal and comparing a resulting second number with the stored divided number;
• providing the first edge on an output clock signal in response to each first edge of the input clock signal;
• and
• providing the second edge on the output clock signal whenever the second number is the same as the stored divided number.