High performance dual-stage sense amplifier circuit

A sense amplifier for a memory device comprising:

• a first sensing stage comprising a first sending device and a second sensing device;
• a first sensing line and a second sense line directly connect to a gate of said first sensing device and a gate of said second sensing device, respectively, to reduce capacitive load on said first sense line and said second sense line;
• wherein a source terminal of said first sensing device and said second sensing device, respectively, is connected to a switchable current sink and a drain terminal of said first sensing device and said second sensing device, respectively, connected to an input of a second sensing stage;
• said second sensing stage comprising cross-coupled inverters responsive to said first sensing stage, said second sensing stage activated by a sense enable signal following a selected delay, wherein said first sensing stage is deactivated once said second sensing stage is activated;
• an output driver responsive to said second sensing stage;
• a precharge of selected dynamic nodes of said sense amplifier;
• wherein said output driver is a high speed push-pull circuit connected to said second sensing stage, said output driver configured to ensure that said precharge deactivates said output driver, and thereby, said sense amplifier exhibits a high impedance state at an output thereof.

A method of detecting a signal on a pair of complementary sense lines in a dual-stage sense amplifier for a memory device comprising:

• detecting a differential voltage between a first sense line and a second sense line with a first sensing stage comprising a first sensing device and a second sensing device;
• amplifying said differential voltage with a second sensing stage comprising cross-coupled inverters responsive to said first sensing stage, said second sensing stage activated by a sense enable signal following a selected delay, wherein said first sensing stage is deactivated once said second sensing stage is activated;
• generating a output signal with as output driver responsive to said second sensing stage;
• and
• deactivating said first sensing stage when said second sensing stage of said sense amplifier is activated so that at any time only one of said first sensing stage and said second sensing stage is active.

A method of detecting a signal an a pair of complementary sense lines in a dual-stage sense amplifier for a memory device comprising;

• detecting a differential voltage between a first sense line and a second sense line with a first sensing stage comprising a first sensing device and a second sensing device;
• amplifying said differential voltage with a second sensing stage comprising cross-coupled inverters responsive to said first sensing stage, said second sensing stage activated by a sense enable signal following a selected delay, wherein said first sensing stage is deactivated once said second sensing stage is activated;
• generating a output signal with an output driver responsive to said second sensing stage;
• a precharge of selected dynamic nodes of said sense amplifier, said precharging includes voltage equalization between signal phases of said sensing lines;
• and
• wherein said output driver is a high speed push-pull circuit connected to said second sensing stage, said output driver configured to ensure that said precharging deactivates said output driver, and thereby, said sense amplifier exhibits a high impedance state at an output thereof.

A sense amplifier for a memory device comprising:

• first sensing stage comprising a first sensing device and a second sensing device;
• a first sense line and a second sense line directly connected to a gate of said first sensing device and a gate of said second sensing device, respectively, to reduce capacitive load on said first sense line and said second sense line;
• wherein a source terminal of said first sensing device and said second sensing device, respectively, is connected to a switchable current sink and a drain terminal of said first sensing device and said second sensing device, respectively, connected to an input of a second sensing stage;
• said second sensing stage comprising a pair of cross-coupled complementary inverters coupled to said switchable current sink, responsive to said first sensing stage and operably connected to said first sense line and said second sense line, said second sensing stage activated by a sense enable signal;
• an output driver responsive to said second sensing stage;
• a precharge of selected dynamic nodes of said sense amplifier;
• and
• wherein said output driver is a high speed push-pull circuit connected to said second sensing stage, said output driver configured to ensure that said precharged deactivates said output driver, and thereby, said sense amplifier exhibits a high impedance stage at an output thereof.

A sense amplifier for a memory device comprising:

• first sensing stage comprising a first sensing device and a second device;
• a first sense line and a second sense line directly connected to a gate of said first sensing device and a gate of said second sensing device, respectively, to reduce capacitive load on said first sense line and said second sense line;
• wherein a source terminal of said first sensing device and said second sensing device, respectively, is connected to a switchable current sink and a drain terminal of said first sensing device and said second sensing device, respectively, connected to an input of a second sensing stage;
• said second sensing stage comprising a pair of cross-coupled complementary inverters coupled to said switchable current sink, responsive to said first sensing stage and operably connected to said first sense line and said second sense line, said second sensing stage activated by a sense enable signal;
• an output driver responsive to said second sensing stage;
• a precharge of selected dynamic nodes of said sense amplifier;
• and
• wherein said output driver is a pair of high speed CMOS inverter circuits connected to said second sensing stage, said output driver configured to ensure that said precharged deactivates said output driver, and thereby, said sense amplifier exhibits a dynamic true and complement state at an output thereof.

A method of detecting a signal on a pair of complementary sense lines in a dual-stage sense amplifier for a memory device comprising:

• detecting a differential voltage between a first sense line and a second sense line with a first sensing stage comprising a first sensing device and a second sensing device;
• amplifying said differential voltage with a second sensing stage comprising cross-coupled inverters responsive to and in parallel with said first sensing stage, said second sensing stage activated by a sense enable signal;
• generating a output signal with as output driver responsive to said second sensing stage;
• and
• wherein said output driver is a high speed push-pull circuit connected to said second sensing stage, said output driver configured to ensure that said precharged deactivates said output driver, and thereby, said sense amplifier exhibits a high impedance state at an output thereof.