Clock signal feeding circuit
AssigneeOki Electric Industry Co., Ltd.
InventorNobuyuki Endo
Life of this patent
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Abstract
The present invention provides a clock signal feeding circuit that suppresses performance degradation under the worst operating conditions. A clock signal CLK is fed, via a delay buffer with a capacitor as a delay element, to a FF disposed in the upstream of a logic circuit block having the longest processing time, and a clock signal CLK is fed, via a delay buffer with a transistor as a delay element, to a FF disposed in the downstream of the logic circuit block having the longest processing time. If the processing time of the logic circuit block increases due to factors such as variations in operating environment, and thus outputting of data representing the operation result delays, the timing of the clock signals fed to the FFs also delays due to the same factors.
Claims11
A clock signal feeding circuit for feeding common clock signals to flip-flops that transmit and receive data between a plurality of logic circuit blocks, which form a semiconductor logic circuit, the clock signal feeding circuit comprising:
- a first delay buffer for feeding the clock signals to a first flip-flop, which passes data to a critical block with the longest processing time among those of the plurality of logic circuit blocks, said clock signals fed using at least one delay element of which variation in delay time resulting from variations in an operating environment or a manufacturing process is less than that of a critical block;
- and
- a second delay buffer for feeding the clock signals to a second flip-flop, which receives data from the critical block, said clock signals fed using delay elements of which variation in delay time resulting from an operating environment or a manufacturing process is substantially equal to variation in delay time of the critical block.
A clock signal feeding circuit, comprising:
- a first logic circuit block, which forms a semiconductor logic circuit;
- a second logic circuit block, which forms said semiconductor logic circuit altogether with said first logic circuit block and conducts processing in processing time shorter than that of said first logic circuit block;
- a first latch circuit, which outputs data to said first logic circuit block;
- a second latch circuit, which receives data outputted from said first logic circuit block and then outputs data to said second logic circuit block;
- a clock terminal provided at each of said first and second latch circuits;
- a clock signal line, which is connected to each of the clock terminals, and to which said clock signals are inputted;
- a first delay buffer, which is connected between said clock signal line and said first latch circuit, and is formed from a delay element of which variation in processing time that is affected by an operating environment or a manufacturing process is smaller than variation in processing time that is affected by an operating environment or a manufacturing process in said first logic circuit block;
- and
- a second delay buffer, which is connected between said clock signal line and said second latch circuit, and is formed from a delay element of which variation in processing time that is affected by an operating environment or a manufacturing process is at least substantially equal to variation in processing time that is affected by an operating environment or a manufacturing process in said first logic circuit block.
A clock signal feeding circuit, comprising:
- a clock signal input terminal into which a TC cycle clock signal is inputted;
- a first latch circuit having a clock terminal into which a clock signal for controlling timing of outputting data is inputted;
- a semiconductor logic circuit block, which inputs data from said first latch circuit and processes the data in processing time TPS;
- a second latch circuit, which inputs data from said semiconductor logic circuit block and has a clock terminal into which a clock signal for controlling timing of outputting data is inputted;
- a first delay buffer, which is provided between said first latch circuit and said clock signal input terminal, said first delay buffer delaying the clock signal so that the clock signal inputted at said clock signal input terminal is synchronously inputted to the clock terminal of said first latch circuit and to the clock terminal of said second latch circuit;
- and
- a second delay buffer, of which variation in delay time resulting from variations in an operating environment or in a manufacturing process is by ΔTC longer than such variations in said first delay buffer, the second delay buffer being provided between said second latch circuit and said clock signal input terminal, and delaying the clock signal so that the clock signal inputted at said clock signal input terminal is simultaneously inputted to the clock terminal of said first latch circuit and to the clock terminal of said second latch circuit,
- wherein, when the variation in delay time resulting from variations in an operating environment or a manufacturing process is denoted by ΔTP, wherein TPS+ΔTP<TC+ΔTC.
Dependencies are inferred from the claim text.