US 6,788,107 B2Granted

Variable voltage tolerant input/output circuit

AssigneeBrilliance Semiconductor, Inc.

InventorChih-hsien Wang

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Abstract

A variable voltage tolerant input/output circuit, wherein a leakage current is not produced while having a high reliability, characterized in that the circuit includes a clamping circuit for clamping the N-well potential of M1. When the supply voltage VCC is higher than or equal to the input/output voltage VI/O, the N-well potential of M1 is clamped to the supply voltage VCC; when the supply voltage VCC is lower than the input/output voltage VI/O, the N-well potential of M1 is clamped to the input/output voltage VI/O.

Claims3

Dependent claims

A variable voltage tolerant input/output circuit comprising:

a supply voltage;
a ground voltage;
a first PMOS transistor, with one of its P+ regions coupled via an electrode to the supply voltage, while the other P+ region coupled via an electrode to an output circuit;
a second PMOS transistor, with one of its P+ regions coupled via an electrode to the supply voltage, while the other P+ region coupled to the gate of the first PMOS transistor, and its gate coupled to an input control circuit;
a third PMOS transistor, with its source coupled to the supply voltage, and its gate coupled to another input control circuit;
a first NMOS transistor, with its drain coupled to the output circuit, its source coupled to the ground voltage, and its gate coupled to the drain of the third PMOS transistor;
a second NMOS transistor, with its drain coupled to the gate of the first PMOS transistor, its source coupled to the ground voltage, and its gate coupled to the gate of the second PMOS transistor;
a third NMOS transistor, with its drain coupled to the gate of the first NMOS transistor, its source coupled to the ground voltage, and its gate coupled to the gate of the third PMOS transistor;
and
characterized in that the variable voltage tolerant input/output circuit further comprises a clamping circuit including,
a fourth PMOS transistor, with its gate coupled to the N-well of the first PMOS transistor, and one of its P+ regions coupled via an electrode to the supply voltage, while the other P+ region coupled via an electrode to the N-well of the first PMOS transistor;
and
a fifth PMOS transistor, with its gate coupled to the N-well of the first PMOS transistor, and one of its P+ regions coupled via an electrode to the N-well of the first PMOS transistor, while the other P+ region coupled via an electrode to the output circuit, wherein the P+ region of the second PMOS transistor originally coupled via an electrode to the supply voltage is replaced by the N-well coupled via an electrode to the first PMOS transistor.

10 more elements

Dependencies are inferred from the claim text.

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Abstract

A variable voltage tolerant input/output circuit comprising:

a supply voltage;
a ground voltage;
a first PMOS transistor, with one of its P+ regions coupled via an electrode to the supply voltage, while the other P+ region coupled via an electrode to an output circuit;
a second PMOS transistor, with one of its P+ regions coupled via an electrode to the supply voltage, while the other P+ region coupled to the gate of the first PMOS transistor, and its gate coupled to an input control circuit;
a third PMOS transistor, with its source coupled to the supply voltage, and its gate coupled to another input control circuit;
a first NMOS transistor, with its drain coupled to the output circuit, its source coupled to the ground voltage, and its gate coupled to the drain of the third PMOS transistor;
a second NMOS transistor, with its drain coupled to the gate of the first PMOS transistor, its source coupled to the ground voltage, and its gate coupled to the gate of the second PMOS transistor;
a third NMOS transistor, with its drain coupled to the gate of the first NMOS transistor, its source coupled to the ground voltage, and its gate coupled to the gate of the third PMOS transistor;
and
characterized in that the variable voltage tolerant input/output circuit further comprises a clamping circuit including,
a fourth PMOS transistor, with its gate coupled to the N-well of the first PMOS transistor, and one of its P+ regions coupled via an electrode to the supply voltage, while the other P+ region coupled via an electrode to the N-well of the first PMOS transistor;
and
a fifth PMOS transistor, with its gate coupled to the N-well of the first PMOS transistor, and one of its P+ regions coupled via an electrode to the N-well of the first PMOS transistor, while the other P+ region coupled via an electrode to the output circuit, wherein the P+ region of the second PMOS transistor originally coupled via an electrode to the supply voltage is replaced by the N-well coupled via an electrode to the first PMOS transistor.

10 more elements