Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data

An integrated circuit device, comprising:

• a data inversion circuit that is configured to evaluate at least first and second ordered groups of input data in parallel with a last ordered group of output data previously generated by said data inversion circuit, and is further configured to output inverted versions of the first and second ordered groups of input data whenever a number of bit differences between the first ordered group of input data and the last ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the inverted version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

A dual data rate (DDR) memory device, comprising:

• a memory cell array that is configured to support a 4-bit prefetch operation in response to a read instruction;
• and
• a data inversion circuit that is configured to evaluate bit differences between first and second ordered groups of data received in parallel at inputs thereof by performing bit-to-bit comparisons between corresponding bits in the first and second ordered groups of data, and is further configured to generate a version of the first ordered group of data in parallel with an inverted version of the second ordered group of data at outputs thereof when a number of bit differences between the version of the first ordered group of data and the second ordered group of data is greater than one-half the number of bits of data within the second ordered group of data.

An integrated circuit device, comprising:

• a data inversion circuit that is configured to evaluate at least first and second ordered groups of current input data in parallel with an ordered group of prior output data, said data inversion circuit comprising logic that is configured to output inverted or non-inverted versions of the first and second ordered groups of current input data as first and second ordered groups of current output data, respectively, in order to maintain a number of bit inversions between the ordered group of prior output data and the first ordered group of current output data at less than or equal to one-half a size of the first ordered group of current output data and also maintain a number of bit inversions between the first ordered group of current output data and the second ordered group of current output data at less than or equal to one-half a size of the second ordered group of current output data.