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US 6,788,104 B2Granted
Field programmable logic device with efficient memory utilization
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsMoninder Singh, Anurag Chaudhry
Life of this patent
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Abstract
A field programmable logic device includes at least two independently configurable embedded memory structures. The memory structures may differ in at least one parameter, such as memory size, available configuration depths, and available configuration widths. As such, a more efficient memory utilization is provided.
Claims10
A field programmable logic device comprising:
- a plurality of independently configurable, embedded memory structures;
- a plurality of logic interface devices;
- a plurality of routing tracks interconnecting said memory structures and connecting said memory structures to said logic interface devices, each routing track having first and second ends;
- a respective bi-directional programmable buffer connected to the first and second ends of each routing track;
- and
- a plurality of routing channels interconnecting said logic interface devices;
- each of the plurality of logic interface devices comprising a plurality of programmable switches connecting said routing tracks to said routing channels;
- said memory structures differing with respect to a configuration parameter comprising at least one of memory size, available memory configuration depth, and available memory configuration width, and said memory structures being configurable in a plurality of mutually exclusive configuration modes.
5 more elements
A field programmable logic device comprising:
- a plurality of independently configurable, multi-port, embedded memory structures;
- and
- a plurality of logic interface devices;
- a plurality of routing tracks interconnecting said memory structures and connecting said memory structures to said logic interface devices, each routing track having first and second ends;
- a respective bi-directional programmable buffer connected to the first and second ends of each routing track;
- and
- a plurality of routing channels interconnecting said logic interface devices;
- each of the plurality of logic interface devices comprising a plurality of programmable switches connecting said routing tracks to said routing channels;
- said memory structures differing with respect to a configuration parameter comprising at least one of memory size, available memory configuration depth, and available memory configuration width, and said memory structures being configurable in a plurality of mutually exclusive configuration modes.
6 more elements
A method for making a programmable logic device comprising:
- forming a plurality of independently configurable, embedded memory structures, the memory structures differing with respect to a configuration parameter thereof, and the memory structures being configurable in a plurality of mutually exclusive configuration modes;
- providing a plurality of logic interface devices;
- interconnecting said memory structures and connecting said memory structures to said logic interface devices with a plurality of routing tracks each having first and second ends;
- connecting a respective bi-directional programmable buffer to the first and second ends of each routing track;
- and
- interconnecting said logic interface devices with a plurality of routing channels;
- each of the plurality of logic interface devices comprising a plurality of programmable switches connecting said routing tracks to said routing channels.
4 more elements
Dependencies are inferred from the claim text.