US 6,788,100 B2Granted

Resistor mirror

AssigneeBlueheron Semiconductor Corporation

InventorAlan Fiedler

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Abstract

A resistor mirror which biases transistors substantially in their linear region of operation and in such a way that their combined parallel resistance is equal to the resistance of a reference resistor. The resistor mirror may include three or more offset control circuits, a feedback control circuit with a reference resistor, a reference voltage-controlled resistor, and one or more additional voltage-controlled resistors. The offset control circuit includes two voltage-controlled current sources. Three or more offset control circuits are connected in a manner so as to affect an equal number of resistor control output terminals coupled to the reference voltage-controlled resistor and to the additional voltage-controlled resistors. To minimize signal coupling between multiple voltage-controlled resistors coupled to the same resistor control output terminals, and to insure stability in the circuit's operating point, a filter capacitor is coupled to each resistor control output terminal. Additionally, through transistor scaling, the resistance of any voltage-controlled resistor may be a multiple or fraction of the reference resistor.

Claims16

Dependent claims

A resistor mirror for providing a resistance in proportion to that of a reference resistor, comprising:

first and second power supply terminals;
first, second, and third resistor control output terminals;
a feedback node;
a reference voltage-controlled resistor circuit coupled between the second power supply terminal and the feedback node and having first, second, and third control terminals respectively coupled to the first, second, and third resistor control output terminals;
a second voltage-controlled resistor circuit coupled between the second power supply terminal and a resistor mirror output terminal and having first, second, and third control terminals respectively coupled to the first, second, and third resistor control output terminals;
a feedback control circuit coupled to the first and second power supply terminals, and having first, second, and third control output terminals respectively coupled to the first, second, and third resistor control output terminals, a reference voltage input terminal, and a control input terminal coupled to the feedback node;
a first offset control circuit, having an output terminal coupled to the first resistor control output terminal, a first input terminal coupled to the first power supply terminal, and a second input terminal coupled to the second resistor control output terminal;
a second offset control circuit, having an output terminal coupled to the second resistor control output terminal, a first input terminal coupled to the first resistor control output terminal, and a second input terminal coupled to the third resistor control output terminal;
and
a third offset control circuit, having an output terminal coupled to the third resistor control output terminal, a first input terminal coupled to the second resistor control output terminal, and a second input terminal coupled to the second power supply terminal.

7 more elements

Dependencies are inferred from the claim text.