Test structures for simultaneous switching output (SSO) analysis
AssigneeLSI Logic Corporation
InventorsAlaa A. Alani, Johann Leyrer, Human Boluki
Life of this patent
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Abstract
An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a common delay and (ii) one of a plurality of different staggered delays determined by a stagger signal. The a second circuit may be configured to generate a plurality of first drive signals by gating the intermediate signals with a plurality of enable signals. The a third circuit may be configured to generate a plurality of first output signals at a transmit interface of a chip by buffering the first drive signals.
Claims20
An apparatus comprising:
- a first circuit configured to generate a plurality of intermediate signals from a data signal, each of said intermediate signals switchable between (i) a common delay and (ii) one of a plurality of staggered delays determined by a stagger signal;
- a second circuit configured to generate a plurality of first drive signals by gating said intermediate signals with a plurality of enable signals;
- and
- a third circuit configured to generate a plurality of first output signals at a transmit interface of a chip by buffering said first drive signals.
A method for operating a circuit comprising the steps of:
- (A) generating a plurality of intermediate signals from a data signal, each of said intermediate signals switchable between (i) a common delay and (ii) one of a plurality of staggered delays determined by a stagger signal;
- (B) generating a plurality of first drive signals by gating said intermediate signals with a plurality of enable signals;
- and
- (C) generating a plurality of first output signals at a transmit interface of said circuit by buffering said first drive signals.
A circuit comprising:
- means for generating a plurality of intermediate signals from a data signal, each of said intermediate signals switchable between (i) a common delay and (ii) one of a plurality of different staggered delays determined by a stagger signal;
- means for generating a plurality of first drive signals by gating said intermediate signals with a plurality of enable signals;
- and
- means for generating a plurality of first output signals at a transmit interface by buffering said first drive signals.
Dependencies are inferred from the claim text.