Security improvements for programmable devices
AssigneeXilinx, Inc.
InventorsJesse H. Jenkins, IV, Shankar Lakkapragada
Life of this patent
Estimating the term…
Abstract
A programmable logic device includes a function block to generate a power control signal that is distributed on a rail to selectively power down various components on the device. The rail is coupled to an observation pin to allow for external observation of the power control signal. The power control signal is also provided as a feed forward signal to an input signal blocking circuit, which selectively enables or disables the device input pins in response to the feed forward signal. The feed forward signal is not accessible from the observation pin, and therefore cannot be externally altered from the observation pin.
Claims35
An apparatus for disabling a plurality of input pins of a programmable logic device (PLD), comprising:
- means for generating a power control signal;
- a distributed rail to route the power control signal throughout the PLD;
- an observation pin connected to the distributed rail, the power control signal externally observable via the observation pin;
- a feed forward signal indicative of the logic state of the power control signal, the feed forward signal not being alterable from the observation pin;
- and
- an input signal blocking circuit coupled to the input pins, the input signal blocking circuit for selectively disabling the input pins in response to the feed forward signal.
An apparatus for disabling a plurality of input pins of a programmable logic device (PLD), comprising:
- at least one configurable block, comprising:
- control logic for generating a power control signal;
- a flip-flop having an input to receive the power control signal from the control logic;
- and
- a buffer having an input connected to an output of the flip-flop;
- a power control rail coupled to an output of the buffer for distributing the power control signal throughout the PLD;
- an observation pin connected to the power control rail, the observation pin for allowing external observation of the power control signal;
- a plurality of input pass transistors, each having a gate and coupled between a corresponding input pin and internal logic of the PLD;
- and
- a feed forward path connected between the output of the flip-flop and the gates of the input pass transistors, the feed forward path providing a logic state of the power control signal as a feed forward signal to the input pass transistors.
A method of restricting access to a programmable logic device (PLD) including a plurality of device input pins, the method comprising:
- generating a power control signal;
- providing the power control signal to a distributed rail that is externally observable from a device observation pin;
- providing the power control signal as a feed forward signal to an input signal blocking circuit;
- and
- selectively disabling the device input pins in response to the feed forward signal.
Dependencies are inferred from the claim text.