Method for gross input leakage functional test at wafer sort
AssigneeXilinx, Inc.
InventorsDavid Mark, Randy J. Simmons
Life of this patent
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Abstract
A method and test configuration for performing a gross input leakage test at wafer sort is described. The method uses a pullup and pulldown on an I/O pad to inject current at the I/O pad, and, based on the resulting voltage, determines if the leakage current is excessive. The method allows an input leakage test to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.
Claims17
A test configuration comprising:
- an integrated circuit to be tested;
- an I/O pad of the integrated circuit;
- a resistive element on the integrated circuit coupled between the I/O pad and a voltage reference node;
- and
- a detector on the integrated circuit for detecting a logic level of the I/O pad, wherein the resistive element is a first transistor, and wherein the voltage reference node is a power node, further comprising:
- a second transistor coupled between the input pad and a ground node;
- a memory bit coupled to a gate of the first transistor;
- and
- a memory bit coupled to a gate of the second transistor.
A method for testing leakage current between an input pad of an integrated circuit and a voltage reference node, the method comprising:
- enabling a resistive element on the integrated circuit coupled between the input pad and the voltage reference node;
- after enabling the resistive element, detecting a logic value of the input pad;
- and
- determining the leakage current based on the detected logic value.
A test configuration comprising:
- an integrated circuit to be tested;
- an I/O pad of the integrated circuit;
- a resistive element on the integrated circuit coupled between the I/O pad and a voltage reference node;
- and
- a detector on the integrated circuit for detecting a leakage current of the I/O pad.
Dependencies are inferred from the claim text.