Fault tolerant semiconductor system

A semiconductor system comprising:

• a plurality of semiconductor chips,
• a first group of wirings which interconnect said plurality of semiconductor chips,
• a second group of wirings for redundancy which interconnect said plurality of semiconductor chips, and
• a connection rearrange wiring section including a connection test circuit which makes a test for connection between said plurality of semiconductor chips by said first group of wirings and a connection rearrange circuit which makes unusable the wiring of said first group in which poor connection occurs and rearranges the connection between said semiconductor chips by use of the wiring of said second group when the poor connection is detected in the wiring of said first group by said connection test circuit, wherein said connection test circuit includes a test data storage element which stores test data and a test result storage element which stores a test result, connection tests are made for said first group of wirings by use of the test data stored in said test data storage element and the test results are stored in said test result storage element.

A connection test method which is used for a semiconductor system in which a plurality of semiconductor chips are interconnected via wirings, the plurality of semiconductor chips including a connection rearrange wiring section configured by a plurality of blocks each including a connection test circuit and connection rearrange circuit, and a connection test control circuit including a test data generating circuit which generates test data and a coincidence determination circuit which detects whether or not poor connection occurs, and the connection test circuit including a test data storage element which stores test data and a test result storage element which stores the test result and making a connection test for the wirings at the time of boot by control of the connection test control circuit, comprising:

• initializing the test result storage elements in the connection test circuits,
• generating test data by use of the test data generating circuit, writing the test data into the test data storage elements connected via scan paths,
• transferring and writing test data between the test data storage elements of the plurality of semiconductor chips via the wirings between the semiconductor chips,
• sequentially reading out values of the test data storage elements provided in the blocks of the plurality of semiconductor chips via the scan paths and sequentially writing the results of coincidence determination made by the coincidence determination circuit into the test data storage elements,
• recording the results of the connection tests stored in the test data storage elements into the test result storage elements of the respective blocks,
• repeatedly performing an operation of said recording of the test data to said recording of the test result into the test result storage elements with respect to a required test pattern,
• writing values of the test data storage elements into the test result storage elements of the respective blocks, and
• transferring the test result written into the test result storage element to the connection test control circuit via the scan path to determine pass/fail of the connection.