Method and apparatus for calibrating a delay locked loop charge pump current
AssigneeSun Microsystems, Inc.
InventorsClaude R. Gauthier, Brian W. Amick, Pradeep Trivedi, Dean Liu
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Abstract
A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.
Claims21
An integrated circuit, comprising:
- a clock path for carrying a clock signal;
- a power supply path adapted to receive power from a power supply;
- a delay locked loop connected to the power supply path, comprising:
- a phase detector that detects a phase difference between the clock signal and a delayed clock signal,
- charge pump, responsive to the phase detector, that outputs a current on a control signal,
- a bias generator, responsive to the control signal, that generates a bias voltage, and
- a voltage-controlled delay line, responsive to the bias voltage, that generates the delayed clock signal;
- an adjustment circuit operatively connected to the charge pump, wherein the adjustment circuit is responsive to control information to adjust the current output from the charge pump;
- and
- a storage device adapted to store the control information to which the adjustment circuit is responsive.
A method for post-fabrication treatment of a delay locked loop, comprising:
- generating a delayed clock signal using a voltage-controlled delay line;
- comparing the delayed clock signal to a clock signal;
- generating a current signal using a charge pump responsive to the comparing;
- selectively adjusting the current signal using an adjustment circuit operatively connected to the charge pump;
- generating a bias voltage to the voltage-controlled delay line dependent on the selectively adjusting;
- and
- storing control information determined from the selectively adjusting.
An integrated circuit, comprising:
- delay locked loop means for generating a delayed clock signal, wherein the delay locked loop means comprises:
- comparing means for detecting a phase difference between a clock signal and the delayed clock signal,
- charge pumping means for generating a current on a control signal, wherein the charge pumping means is responsive to the comparing means,
- bias generating means for generating a bias voltage, wherein the bias generating means is responsive to the control signal, and
- delaying means for generating the delayed clock signal, wherein the delaying means is responsive to the bias voltage;
- adjusting means for selectively adjusting the current output from the charge pump, wherein the charge pumping means is responsive to the adjusting means;
- and
- storing means for storing control information determined using the adjusting means.
Dependencies are inferred from the claim text.