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US 6,787,906 B1Granted
Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region
AssigneeSamsung Electronics Co., Ltd.
InventorsWon-Suk Yang, Sang-Ho Song, Hong-Sik Jeong, Ki-Nam Kim
Life of this patent
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Abstract
An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.
Claims11
A semiconductor device comprising:
- a first dielectric layer formed on a substrate;
- a second dielectric layer formed on the first dielectric layer;
- a stud formed through the first and second dielectric layers;
- a third dielectric layer on the second dielectric layer having an opening above a top of the stud and being spaced apart from the stud;
- and
- a first pad of first etch stop material formed in an undermined region of the second dielectric layer below a portion of a lower surface of the third dielectric layer and above a portion of an upper surface of the first dielectric layer, the undermined region being formed after removal of a portion of the second dielectric layer.
3 more elements
Dependencies are inferred from the claim text.