Package structure with increased capacitance and method
AssigneeIntel Corporation
InventorMahadevan Survakumar
Life of this patent
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Abstract
A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.
Claims25
A package structure comprising:
- a buildup layer comprised of a buildup layer dielectric with ablated regions therein thinning the buildup layer in the ablated regions;
- and
- buildup layer conductive material disposed over the buildup layer including within the ablated regions of the buildup layer,
- wherein a core outer conductive layer and the buildup layer conductive material provide capacitance therebetween, the thinner buildup layer in the ablated regions increasing the capacitance.
A package comprising:
- a core having an inner dielectric portion and a core outer conductive layer;
- a plurality of buildup layers disposed over the core, the buildup layers having offset ablated regions to reduce a thickness of the buildup layers in the ablated regions, the buildup layers having conductive material disposed thereon including within the ablated regions, the reduced thickness serving to increase a capacitance between adjacent of the buildup layers.
A system comprising:
- a processor included on a substrate;
- a package structure coupled to power pins and I/O pins of the processor;
- and
- a circuit board coupled with package structure,
- wherein the package structure comprises:
- a plurality of buildup layers disposed over a core, the buildup layers having offset ablated regions to thin the buildup layers in the ablated regions, the buildup layers having conductive material disposed thereon including within the ablated regions providing capacitance therebetween, the thinner buildup layers in the ablated regions increasing the capacitance.
Dependencies are inferred from the claim text.