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US 6,787,886 B1Granted
Semiconductor device and methods of fabricating the same
AssigneeOki Electric Industry Co., Ltd.
InventorsKazuhiko Asakawa, Wataru Shimizu
Life of this patent
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Abstract
A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.
Claims13
A semiconductor device comprising:
- a semiconductor substrate which has first and second regions formed on a major surface thereof;
- a first insulating layer which is formed over the first region;
- a dummy pattern which has a predetermined shape and which is formed on said first insulating layer;
- a first SOG layer which is formed on side surfaces of said dummy pattern and the first insulating layer;
- a second SOG layer which is formed on a top surface of said dummy pattern and said first SOG layer, said second SOG layer being denser than said first SOG layer;
- and
- a second insulating layer which is formed on said second SOG layer;
- wherein said first and second insulating layers and said first and second SOG layers are exposed at a boundary between the first region and the second region.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate which has first and second regions formed on a major surface thereof, the second region surrounding the fist region;
- a first insulating layer which is formed over the second region;
- a dummy pattern which has a frame shape surrounding the first region and which is formed on said first insulating layer;
- a first SOG layer which is formed on side surfaces of said dummy pattern and the first insulating layer;
- a second SOG layer which is formed on a top surface of said dummy pattern and said first SOG layer, said second SOG layer being denser than said first SOG layer;
- and
- a second insulating layer which is formed on said second SOG layer;
- wherein said first and second insulating layers and said first and second SOG layers are exposed at a boundary between the first region and the second region.
5 more elements
A semiconductor memory device, comprising:
- a semiconductor substrate, which has a first region and a second region formed on a major surface thereof;
- a first insulating layer, which is formed over the first region;
- a dummy pattern, which has a predetermined shape, and which is formed on said first insulating layer;
- a first SOG layer, which is formed in side surfaces of said dummy pattern and said first insulating layer;
- a second SOG layer, which is formed on a top surface of said dummy pattern and said first SOG layer, said second SOG layer being denser than said first SOG layer;
- and
- a second insulating layer, which is formed on said second SOG layer, wherein said first and second insulating layers and said first and second SOG layers are exposed at a boundary between the first region and the second region.
4 more elements
Dependencies are inferred from the claim text.