Semiconductor memory device with shortened connection length among memory block, data buffer and data bus

A semiconductor memory device comprising:

• eight memory blocks arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area;
• a first data bus having a plurality of data lines and linearly extending between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix;
• and
• a second data bus having a plurality of data lines and linearly extending between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix,
• wherein the eight memory blocks have a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus,
• wherein the first data bus is for the memory block having an even column address, and the second data bus is for the memory block having an odd column address,
• wherein the eight memory blocks have two groups each including four memory blocks having the even or odd column address, the first group is arranged adjacent the first data bus and connected to the first data bus, and the second group is arranged adjacent the second data bus and connected to the second data bus.

A semiconductor memory device comprising:

• eight memory blocks arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area;
• a first data bus having a plurality of data lines and linearly extending between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix;
• a second data bus having a plurality of data lines and linearly extending between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix,
• a first data buffer arranged within the center area adjacent memory blocks in the first row of the matrix and connected to the first data bus;
• a second data buffer arranged within the center area adjacent memory blocks in the third row of the matrix and connected to the second data bus;
• a first perpendicular bus extending perpendicular to a longitudinal direction of the second data bus, the first perpendicular bus being connected between the second data bus and the first data buffer;
• and
• a second perpendicular bus extending perpendicular to a longitudinal direction of the first data bus, the first perpendicular bus being connected between the first data bus and the second data buffer,
• wherein the eight memory blocks have a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.

A semiconductor memory device comprising:

• eight memory blocks arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area;
• a first data bus having a plurality of data lines and linearly extending between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix;
• and
• a second data bus having a plurality of data lines and linearly extending between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix,
• wherein the eight memory blocks have a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus,
• wherein each of the first and second data buses comprises a data bus equalizer.

A semiconductor memory device comprising:

• eight memory blocks arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area;
• a first data bus having a plurality of data lines and linearly extending between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix;
• and
• a second data bus having a plurality of data lines and linearly extending between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix,
• wherein the eight memory blocks have a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus,
• wherein the eight memory blocks include four banks each having a pair of memory blocks, the one memory block of the bank is connected to the first data bus, the other memory block is connected to the second data bus,
• wherein the eight memory blocks are arranged such that four line segments connected between a pair of memory blocks have no crossing,
• wherein each pair of memory blocks of the bank has a row controller for controlling the row decoder in common.

A semiconductor memory device comprising:

• eight memory blocks arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area;
• a first data bus having a plurality of data lines and linearly extending between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix;
• a second data bus having a plurality of data lines and linearly extending between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix,
• a column decoder associated with a memory block;
• and
• a column controller for controlling the column decoder, the column controller being arranged within the center area adjacent the memory block,
• wherein the eight memory blocks have a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.