Semiconductor devices and methods of manufacturing the same

A semiconductor device comprising:

• a silicon substrate having a first conductivity type;
• a first well of said first conductivity type in said substrate;
• a second well of a second conductivity type adjacent to said first well in said substrate;
• a third well of said first conductivity type formed within a portion of said second well, wherein said third well is isolated from said first well by said second well;
• a first field effect transistor formed in said first well, said first field effect transistor comprising a first gate insulating layer provided in said first well, a first gate electrode on said first gate insulating layer, a first offset LOCOS layer adjacent to said first gate insulating layer, a first offset impurity layer comprising a low density impurity layer of the second conductivity type formed in said silicon substrate under said first offset LOCOS layer, and a first high density impurity layer of the second conductivity type provided adjacent to said first offset LOCOS layer to serve as source/drain areas;
• a second field effect transistor formed in said second well, said second field effect transistor comprising a second gate insulating layer provided in the second well, a second gate electrode on the second gate insulating layer, a second offset LOCOS layer adjacent to said second gate insulating layer, a second offset impurity layer comprising a low density impurity layer of said first conductivity type formed in said silicon substrate under said second offset LOCOS layer, and a second high-density impurity layer of the first conductivity type provided adjacent to said second offset LOCOS layer to serve as source/drain areas;
• a third field effect transistor formed in said third well, said third field effect transistor comprising a third gate insulating layer provided in said third well, a third gate electrode on said third gate insulating layer, a third offset LOCOS layer adjacent to said third gate insulating layer, a third offset impurity layer comprising a low density impurity layer of the second conductivity type formed in said silicon substrate under said third offset LOCOS layer, and a third high density impurity layer of said second conductivity type provided adjacent to said third offset LOCOS layer to serve as source/drain areas;
• a first LOCOS isolation layer positioned between and electrically separating said first and second field effect transistors;
• and
• a second LOCOS isolation layer positioned between and electrically separating said second and third field effect transistors.

A semiconductor device comprising:

• a first well formed in a semiconductor substrate and having a first conductivity type;
• a second well formed in said semiconductor substrate adjacent to said first well and having a second conductivity type;
• a third well formed in said second well and having the first conductivity type;
• and
• a first gate insulating area in the first well;
• a first gate electrode on the first gate electrode in the first well;
• first offset LOCOS regions positioned to sides of the first gate insulating area;
• first offset low density impurity regions positioned in the semiconductor substrate in the first well under the first offset LOCOS regions;
• first high density impurity regions positioned in the semiconductor substrate in the first well and adapted to act as source or drain regions, wherein one of the first offset low density impurity regions extends to one of the first high density impurity regions, and another of the first offset low density impurity regions extends to another of the first high density impurity regions;
• a second gate insulating area in the second well;
• a second gate electrode on the second gate electrode in the second well;
• second offset LOCOS regions positioned to sides of the second gate insulating area;
• second offset low density impurity regions positioned in the semiconductor substrate in the second well under the second offset LOCOS regions;
• second high density impurity regions positioned in the semiconductor substrate in the second well and adapted to act as source or drain regions, wherein one of the second offset low density impurity regions extends to one of the second high density impurity regions, and another of the second offset low density impurity regions extends to another of the second high density impunity regions;
• a third gate insulating area in the third well;
• a third gate electrode on the third gate electrode in the third well;
• third offset LOCOS regions positioned to sides of the third gate insulating area;
• third offset low density impurity regions positioned in the semiconductor substrate in the third well under the third offset LOCOS regions;
• third high density impurity regions positioned in the semiconductor substrate in the third well and adapted to act as source or drain regions, wherein one of the third offset low density impurity regions extends to one of the third high density impurity regions, and another of the third offset low density impurity regions extends to another of the third high density impurity regions;
• a first LOCOS isolation area extending over a portion of the first well and the second well;
• an additional low density impurity region in the first well and positioned under the first LOCOS isolation layer, wherein one of the first high density impurity regions is positioned between one of the first offset low density impurity regions and the additional low density impurity region in the first well;
• a first channel stopper low density impurity region in the first well, the channel stopper low density impurity region positioned under the first LOCOS isolation layer and in contact with the additional low density impurity region in the first well, the first channel stopper low density impurity region having a different conductivity type than the additional low density impurity region in the first well;
• an additional low density impurity region in the second well and positioned under the first LOCOS isolation layer, wherein one of the second high density impurity regions is positioned between one of the second offset low density impurity regions and the additional low density impurity region in the second well;
• and
• a second channel stopper low density impurity region in the second well, the second channel stopper low density impurity region positioned under the first LOCOS isolation layer and between the additional low density impurity region in the second well and the first channel stopper low density impurity region in the first well, the second channel stopper low density impurity region in the second well having a different conductivity type than the additional low density impurity region in the second well, the second channel stopper low density impurity region in the second well having a different conductivity type than the first channel stopper low density impurity region.