Back to results
US 6,787,835 B2Granted
Semiconductor memories
AssigneeHitachi, Ltd.
InventorsBryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata
Life of this patent
Estimating the term…
Abstract
A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
Claims52
A memory element, comprised of:
- a plurality of word lines;
- a plurality of data lines;
- and
- memory cells at the intersections of the word lines and data lines, each memory cell being comprised of
- a first switch element, and
- a first capacitor element, wherein a first terminal of the first capacitor element is electrically connected to a first terminal of the first switch element at a storage node and a second terminal of the first capacitor elemant connected to a reference potential, wherein said first switch element is adapted to transfer a charge to the charge node based on the voltage of one of said data lines and the storage node is coupled to said one of the data lines by capacitive coupling, and
- further wherein said one data line is adapted to obtain at least two voltage values Vd1 and Vd2, wherein Vd1>Vd2 and, immediately following a write operation to the memory cell, the voltage defined by a stored charge at the storage node is Vs1 when a voltage of the data lines is Vd1, and Vs2 when a voltage of the data lines is Vd2, and wherein Vs1 is smaller than Vs2.
4 more elements
A semiconductor memory element, comprised of:
- a plurality of word lines;
- a plurality of pairs of data lines which are respectively complementary data lines for reading data and writing data;
- and
- memory cells at the intersections of the word lines and said pairs of data lines, each of said memory cells comprising
- two transfer transistors, a first transfer transistor responsible for transferring data from a first storage node to a first of a pair of data lines, and a second transfer transistor responsible for transferring data from a second storage node to the second of the pair of data lines, each transfer transistor being activated by the same word line;
- two storage semiconductor devices with a source region and drain region fabricated from metal or a semiconductor material connected by a channel which is formed by a semiconductor material having a thickness of no more than 5 nanometers on top of an insulating film, the voltage level of said channel being affected by the voltage of a gate electrode of said semiconductor device, further wherein the semiconductor devices are arranged in a cross-coupled inverting fashion to the first and second storage nodes.
3 more elements
A semiconductor memory element comprised of:
- a plurality of word lines;
- a plurality of data lines;
- and
- memory cells at the intersections of word lines and data lines, each of said memory cells comprising a storage transistor with a gate terminal electrically connected to a storage node, and a semiconductor write device activated by a write word line electrically connected to the storage node, wherein
- said semiconductor device has a source region and drain region fabricated from a conductor connected by a channel which is formed by a semiconductor material of a thickness of no more than 5 nanometers on top of an insulating film,
- said conductor is a metal of a semiconductor material and the upper part of the polysilicon drain and source regions of the write transistor has a higher concentration of impurities than the lower part of the polysilicon drain and source regions.
3 more elements
A semiconductor memory element comprised of:
- a plurality of word lines;
- a plurality of data lines;
- and
- memory cells at the intersections of the word lines and data lines, each of said memory cells comprising
- a storage transistor with a gate terminal electrically connected to a storage node and one of a source or drain region is connected to a predetermined potential
- a semiconductor write transistor activated by a write word line electrically connected to the storage node and one of a source or drain region of the semiconductor write transistor is connected to a one of the data lines and the other one of the source or drain region of the semiconductor write transistor is connected to the storage node, wherein said semiconductor write transistor has a source region and drain region fabricated from a conductor connected by a channel which is formed by a semiconductor material of a thickness of no more than 5 nanometers on top of an insulating film, and
- wherein said channel region of the semiconductor write transistor is formed in the vertical direction such that the channel region of the semiconductor write transistor connects the gate terminal of the storage transistor with a metal or polysilicon data line positioned vertically above the gate terminal of the storage transistor.
4 more elements
Dependencies are inferred from the claim text.