Semiconductor device and method for fabricating the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsYasuhiro Shimada, Yoshihisa Kato
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Abstract
A gate electrode and a gate insulating film are formed for each of PMOSFET, NMOSFET and ferroelectric FET. Source/drain regions are defined for the NMOSFET and ferroelectric FET and for the PMOSFET by performing ion implantation processes twice separately. An intermediate electrode connected to the gate electrode of the ferroelectric FET, a ferroelectric film and a control gate electrode are formed over a first interlevel dielectric film. An interconnect layer, which includes first and second interconnects and is connected to the gate electrodes of the CMOS device, is formed on a second interlevel dielectric film. The first and second interconnects are connected to the control gate and intermediate electrodes of the ferroelectric FET, respectively.
Claims6
A semiconductor device comprising:
- a semiconductor substrate;
- an MISFET, which is provided on the semiconductor substrate and includes a gate insulating film, a gate electrode and source/drain regions;
- a ferroelectric FET, which is provided on the semiconductor substrate and includes a ferroelectric film provided over the semiconductor substrate, a control gate electrode provided on the ferroelectric film and source/drain regions;
- a memory circuit block, in which the ferroelectric PET is arranged;
- a control circuit block, in which the MISFET is arranged, for controlling the memory circuit block;
- and
- a logic circuit block, in which the MISFET is arranged, including a processor for transferring data to and from the memory circuit block.
A method for fabricating a semiconductor device, comprising the steps of:
- a) forming a gate insulating film and a gate electrode for each of first- and second-channel-type MISFETs and a ferroelectric FET over a semiconductor substrate;
- b) implanting ions of a dopant for forming source/drain regions from over the gate electrode of the ferroelectric FET and the gate electrode of one of the first- and second-channel-type MISFETs;
- c) implanting ions of another dopant for forming source/drain regions from over the gate electrode of the other MISFET;
- d) forming an interlevel dielectric film covering the gate electrodes of the MISFETs and the ferroelectric FET, forming a contact hole, which passes through the interlevel dielectric to reach the gate electrode of the ferroelectric FET, and then filling the contact hole with a conductor material to form a contact member;
- e) forming an intermediate electrode, a ferroelectric film and a control gate electrode over the interlevel dielectric film so that the intermediate electrode is connected to the contact member and that the ferroelectric film is in contact with an upper surface of the intermediate electrode and that the control gate electrode faces the intermediate electrode with the ferroelectric film interposed therebetween;
- f) forming a memory circuit block, in which the ferroelectric FET is arranged;
- g) forming a control circuit block, in which the MISFET is arranged, for controlling the memory circuit block;
- and
- h) forming a logic circuit block, in which the MISFET is arranged, including a processor for transferring data do and from the memory circuit block.
Dependencies are inferred from the claim text.