Thin film transistor array panel

A thin film transistor array panel for a liquid crystal display comprising:

• a gate wire formed on an insulating substrate and including a plurality of gate lines extending to a first direction, gate electrodes connected to the gate line, and gate pads connected to an end of the gate line;
• a gate insulating layer having contact holes exposing the gate pad and formed in a matrix shape on the gate wire and the substrate;
• a semiconductor layer formed on the gate insulating layer;
• a data wire formed on the semiconductor layer and including a plurality of data lines extending to a second direction crossing the gate line, source electrodes adjacent to the gate electrode, drain electrode separated from the data line and the source electrode and located at the opposite side of the source electrode with respect to the gate electrode, and data pads connected to an end of the data line;
• a conductive pattern including a plurality of first patterns formed on the source electrode and the data line, second patterns formed on the drain electrode, third patterns formed on the data pad, and pixel electrodes connected to the second pattern;
• and
• a passivation layer formed on the conductive pattern, the semiconductor pattern and the substrate, and having a plurality of first openings exposing the pixel electrode, second openings exposing the gate insulating layer between the two adjacent data lines, third openings located on the gate pad, and fourth openings exposing the third pattern,
• wherein the data wire is only formed between the conductive pattern and the semiconductor layer, the semiconductor layer is formed on the whole gate insulating layer except for the portion under the second opening, and the portions of the semiconductor layer under the two adjacent data lines are separated from each other.