Wafer with additional circuit parts in the kerf area for testing integrated circuits on the wafer
AssigneeInfienon Technologies AG
InventorsHelmut Fischer, Alan Morgan
Life of this patent
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AssigneeInfienon Technologies AG
InventorsHelmut Fischer, Alan Morgan
Estimating the term…
Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.
A wafer, comprising:
Dependencies are inferred from the claim text.