Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hsiang Yao, Yun-Cheng Lu
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Abstract
A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process water; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
Claims20
A method for reducing electrical discharges within semiconductor wafers comprising the steps of:
- providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects;
- exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer;
- and,
- limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
A method for reducing time dependent dielectric arcing (TDDA) within a semiconductor process wafer comprising the steps of:
- exposing a photoresist layer overlying the semiconductor process wafer to a source of activating radiation;
- limiting the semiconductor process wafer exposure to visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
Dependencies are inferred from the claim text.