Method of making a high-voltage transistor with buried conduction regions
AssigneePower Integrations, Inc.
InventorsVladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
Life of this patent
Estimating the term…
Abstract
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.
Claims12
A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:
- forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;
- implanting a dopant of the second conductivity type into the laterally extended portion of the well region to form a buried region therein, the buried region being implanted at a depth such that a top portion of the well region is not substantially implanted with the dopant so as to remain to be the first conductivity type in said top portion of the well region, and a first conduction channel is defined above the buried region, a second conduction channel being defined below the buried region;
- forming a drain diffusion region of the first conductivity type in the well region, the drain diffusion region being spaced-apart from the buried region, wherein said top portion of the well region has a thickness of no less than 0.5 μm.
A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:
- forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion with a lateral boundary;
- implanting a dopant of the second conductivity type into the well region to form a buried region therein, a top region of the well region being substantially undoped by the implant so as to remain to be the first conductivity type such that first and second JFET conduction channels are respectively defined in the well region above and below the buried region;
- forming a drain diffusion region of the first conductivity type in the well region, the drain diffusion region being spaced-apart from the buried region;
- forming a source diffusion region in the substrate spaced-apart from the well region;
- and
- forming an insulated gate over the substrate, wherein said top region of the well region has a thickness of no less than 0.5 μm.
A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:
- forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;
- implanting a dopant of the second conductivity type into the laterally extended portion of the well region to form a buried region therein, the implant being performed at a sufficiently high energy such that a top portion of the well region is not substantially doped by the implant so as to remain to be the first conductivity type in said top portion of the well region, the buried region dividing the laterally extended portion of the well region into a first conduction channel in the top portion above the buried region and a second conduction channel below the buried region;
- forming a drain diffusion region of the first conductivity type in the well region, the drain diffusion region being spaced-apart from the buried region, wherein said top portion of the well region has a thickness of no less than 0.5 μm.
Dependencies are inferred from the claim text.