Fully depleted SOI transistor with elevated source and drain
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
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Abstract
A method of manufacturing an integrated circuit utilizes a thin film substrate. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.
Claims20
A method of manufacturing an integrated circuit, the integrated circuit including a thin film transistor on a substrate, the substrate including a thin semiconductor layer, the method comprising steps of:
- providing a sacrificial gate structure on the thin semiconductor layer of the substrate;
- etching the thin semiconductor layer in accordance with the sacrificial gate structure;
- providing an amorphous semiconductor layer above the substrate and over the gate structure;
- removing a portion of the amorphous semiconductor layer to expose the sacrificial gate structure;
- forming a single crystalline semiconductor material from the amorphous semiconductor material;
- siliciding the single crystalline material;
- removing the sacrificial gate structure to form an aperture;
- and
- providing a gate conductor in the aperture.
A method of manufacturing an ultra-large scale integrated circuit including a transistor, the method comprising:
- providing a gate mask structure on a top surface of a thin film, the thin film being above a base layer;
- etching the thin film in accordance with the gate mask structure;
- depositing an amorphous semiconductor material above a top surface of the base layer and the mask structure;
- a removing the semiconductor material to a level below a top surface of the mask structure;
- crystalizing the amorphous semiconductor material;
- siliciding the semiconductor material;
- removing the mask structure to leave an aperture;
- and
- providing a gate conductor in the aperture.
A process of manufacturing transistor including a thin film, a gate structure having a gate dielectric above the thin film and a gate conductor above a portion of the gate dielectric, source and drain regions adjacent the gate structure, and a silicide layer having a top surface above a bottom surface of the gate conductor and below a top surface of the gate conductor, the gate dielectric being at least partially above the top surface of the suicide layer, the process comprising:
- providing a mask structure on a top surface of the thin film, the thin film being above a base layer;
- etching the thin film in accordance with the mask structure;
- depositing an amorphous semiconductor material above the top surface of the base layer and the mask structure;
- removing the amorphous semiconductor material to a level below a top surface of the mask structure;
- crystalizing the amorphous semiconductor material;
- siliciding the crystallized semiconductor material to form the silicide layer;
- removing the mask structure to leave an aperture;
- and
- providing the gate conductor in the aperture.
Dependencies are inferred from the claim text.