Method of making the selection gate in a split-gate flash eeprom cell and its structure

A method for manufacturing a selection gate of a split-gate flash EEPROM cell of which a suspending gate structure having at least a gate oxide/polysilicon/first oxide and a source is formed on a semiconductor substrate, the method comprising the steps of:

• forming a trench in the semiconductor substrate on one side of the suspending gate structure, the trench being located opposite to the source and the sidewall of the trench adjacent to the suspending gate structure being a slant sidewall;
• forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench;
• forming a polysilicon spacer on the sidewall of the inter polysilicon dielectric layer as the selection gate;
• and
• forming a drain on the semiconductor substrate in the trench, the drain being adjacent to the selection gate.