Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance

A method of forming a double-gated transistor, comprising the sequential steps of:

• providing a substrate having an SOI structure formed thereover;
• the SOI structure including a lower SOI oxide layer and an upper SOI silicon layer;
• patterning the SOI silicon layer to form a patterned SOI silicon layer;
• the patterned SOI silicon layer including a source region and a drain region connected by a channel portion;
• forming an encasing oxide layer over the patterned SOI silicon layer to form an encased patterned SOI silicon layer;
• forming a patterned dummy layer over the encased patterned SOI silicon layer;
• the patterned dummy layer having an opening, with exposed side walls, exposing:
• the channel portion of the encased patterned SOI silicon layer;
• and
• portions of the upper surface of the SOI oxide layer;
• forming offset spacers over the exposed side walls of the patterned dummy layer opening;
• etching the SOI oxide layer while minimizing the undercut portions of the upper surface of the SOI oxide layer into the SO oxide layer to form a minimal undercut portions;
• the minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer;
• wherein the undercut portions each protrude from about 0 to 2000 Å under the patterned dummy layer opening;
• forming a conformal oxide layer around the channel portion of the patterned SOI silicon layer;
• forming a gate within the patterned dummy layer opening;
• the gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer;
• and
• removing the patterned dummy layer to form the double-gated transistor.

A method of forming a double-gated transistor, comprising the sequential steps of:

• providing a substrate having an SOI structure formed thereover;
• the SOI structure including a lower SOI oxide layer and an upper SOI silicon layer;
• patterning the SOI silicon layer to form a patterned SOI silicon layer;
• the patterned SOI silicon layer including a source region and a drain region connected by a channel portion;
• forming an encasing oxide layer over the patterned SOI silicon layer to form an encased patterned SOI silicon layer;
• forming a patterned dummy layer over the encased patterned SOI silicon layer;
• the patterned dummy layer having an opening, with exposed side walls, exposing:
• the channel portion of the encased patterned SOI silicon layer;
• and
• portions of the upper surface of the SOI oxide layer;
• forming offset spacers over the exposed side walls of the patterned dummy layer opening;
• etching the SOI oxide layer while minimizing the undercut portions of the upper surface of the SOI oxide layer into the SO oxide layer to form a minimal undercut portions;
• the minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer;
• wherein the undercut portions are formed using a dilute HF etch;
• forming a conformal oxide layer around the channel portion of the patterned SOI silicon layer;
• forming a gate within the patterned dummy layer opening;
• the gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer;
• and
• removing the patterned dummy layer using hot phosphoric acid to form the double-gated transistor.