Semiconductor device and method of manufacture
AssigneeSeiko Epson Corporation
InventorsSatoshi Inoue, Piero Migliorato
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Abstract
A TFT memory 11 is provided with a polysilicon layer 22, wherein each region of the source 22a, the channel 22b and the drain 22c are formed on a substrate 21, and gate oxide films (insulating films) 23 and 25 are formed on the polysilicon layer 22; and a plurality of silicon particles 24 for trapping the charge of injected carriers are placed between the gate oxide films 23 and 25. Specifically, the gate oxide films comprise a first gate oxide film 23 and a second gate oxide film 25 formed on the first gate oxide film 23; the plurality of silicon particles 24 are located between the first gate oxide film 23 and the second gate oxide film 25, and the first gate oxide film 23 is formed in an extremely thin thickness.
Claims8
A method of manufacturing a semiconductor device comprising a first step of forming a semiconductor layer which has a source region, a channel region and a drain region on a substrate;
- and a second step of forming an insulating body, which has granular charge trapping bodies inside to trap the charge of injected carriers, on the semiconductor layer, wherein the second step comprises the steps of:
- forming a first insulating film constituting a portion of the insulating film on the semiconductor layer;
- depositing the granular charge trapping bodies on the first insulating film;
- and
- forming a second insulating film constituting a second portion of the insulating film on the first insulating film while the charge trapping bodies are kept on the first insulating film,
- wherein a density of deposited charged trapping bodies per unit area is about 20%.
Dependencies are inferred from the claim text.