Power distribution architecture for inkjet heater chip

A process for manufacturing a heater chip utilized in a printhead of an ink jet printer, by configuring a silicon substrate having a substrate surface and a device surface opposite the substrate surface including a power portion and a ground portion in opposing relation thereon, including the steps of:

• forming a plurality of driving transistors on the device surface of the substrate, each transistor having associated electrical contact regions thereabout,
• depositing a polysilicon layer on the device surface of the silicon substrate,
• selectively masking and etching the polysilicon layer to form at least one input for each driving transistor and a plurality of electrical connections on the device surface of the substrate,
• forming a dielectric layer atop the polysilicon layer,
• selectively masking and etching the dielectric layer, exposing selected portions of the polysilicon layer,
• forming a resistive layer comprising at least one metallic element therein,
• forming a single conductive layer comprising at least one metallic element therein,
• selectively masking and etching the resistive and conductive layers, defining a plurality of resistive heating devices at locations where the conductive layer is etched only to the resistive layer, and a plurality of electrical connections defined by a dual layer structure of resistive and conductive material, wherein the dual layer structure electrically connects the resistive heating elements to a ground and a power structure defined by the etched dual layer structure,
• applying a protective layer of material to cover selected portions of the dual layer metallic structure and the resistive beating devices with the protective layer of material for protecting the dual layer structure and resistive heating elements from ink contamination, and
• forming a spaced array of ink vias through the heater chip, wherein the number of ink vias correspond to a number of resistive heating elements.